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9DB403DGILFT

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19
IDT
®
Four Output Differential Buffer for PCIe Gen 1 and Gen 2 ICS9DB403D REV R 11/1/12
ICS9DB403D
Four Output Differential Buffer for PCIe for Gen 1 and Gen 2
7
Electrical Characteristics - DIF 0.7V Current Mode Differential Pair
T
A
=Tambient; V
DD
= 3.3 V +/-5%; C
L
=2pF, R
S
=33
Ω
, R
P
=49.9
Ω
, R
RE
F
=475
Ω
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Current Source Output
Impedance
Zo
1
3000
Ω
1
Voltage High VHigh 660 850 1,2
Voltage Low VLow -150 150 1,2
Max Volta
g
e Vovs 1150 1
Min Voltage Vuds -300 1
Crossing Voltage (abs) Vcross(abs) 250 550 mV 1
Crossing Voltage (var) d-Vcross
Variation of crossing over all
ed
g
es
140 mV 1
Rise Time t
r
V
OL
= 0.175V, V
OH
= 0.525V 175 700 ps 1
Fall Time t
f
V
OH
= 0.525V V
OL
= 0.175V 175 700 ps 1
Rise Time Variation d-t
r
125 ps 1
Fall Time Variation d-t
f
125 ps 1
Duty Cycle d
t3
Measurement from differential
wavefrom
45 55 % 1
t
p
dBYP
Bypass Mode, V
T
= 50% 2500 5000 ps 1
t
p
dPLL
PLL Mode V
T
= 50% -250 250 ps 1
Skew, Output to Output t
sk3
V
T
= 50% 50 ps 1
PLL mode 50 ps 1,3
Additive Jitter in Bypass Mode 50 ps 1,3
PCIe Gen1 phase jitter
(Additive in B
y
pass Mode)
710
ps
(pk2pk)
1,4,5
PCIe Gen 2 Low Band phase jitter
(Additive in Bypass Mode)
00.1
ps
(rms)
1,4,5
PCIe Gen 2 High Band phase jitter
(Additive in Bypass Mode)
0.3 0.5
ps
(rms)
1,4,5
PCIe Gen 1 phase jitter 40 86
ps
(pk2pk)
1,4,5
PCIe Gen 2 Low Band phase jitter 1.5 3
ps
(rms)
1,4,5
PCIe Gen 2 High Band phase jitter
2.7/
2.2
3.1
ps
(rms)
1,4,5,6
1
Guaranteed b
y
desi
g
n and characterization, not 100% tested in production.
2
I
RE
F
= V
DD
/(3xR
R
). For R
R
= 475
Ω
(1%), I
RE
F
= 2.32mA. I
OH
= 6 x I
RE
F
and V
OH
= 0.7V @ Z
O
=50
Ω
.
3 Measured from differential waveform
4
See http://www.pcisig.com for complete specs
5
Device driven by 932S421C or equivalent.
6
First number is High Bandwidth Mode, second number is Low Bandwidth Mode
Statistical measurement on single
ended signal using oscilloscope
math function.
mV
Measurement on single ended
signal using absolute value.
mV
t
jphaseBYP
Jitter, Phase
t
jphasePLL
Skew, Input to Output
Jitter, Cycle to cycle t
jcyc-cyc
IDT
®
Four Output Differential Buffer for PCIe Gen 1 and Gen 2 ICS9DB403D REV R 11/1/12
ICS9DB403D
Four Output Differential Buffer for PCIe for Gen 1 and Gen 2
8
Clock Periods Differential Outputs with Spread Spectrum Enabled
1 Clock 1us 0.1s 0.1s 0.1s 1us 1 Clock
Lg- -SSC -ppm error 0ppm + ppm error +SSC Lg+
Absolute
Period
Short-term
Avera
g
e
Long-Term
Avera
g
e
Period
Long-Term
Avera
g
e
Short-term
Avera
g
e
Period
Minimum
Absolute
Period
Minimum
Absolute
Period
Minimum
Absolute
Period
Nominal Maximum Maximum Maximum
DIF 100
9.87400 9.99900 9.99900 10.00000 10.00100 10.05130 10.17630 ns 1,2,3
DIF 133
7.41425 7.49925 7.49925 7.50000 7.50075 7.53845 7.62345 ns 1,2,4
DIF 166
5.91440 5.99940 5.99940 6.00000 6.00060 6.03076 6.11576 ns 1,2,4
DIF 200
4.91450 4.99950 4.99950 5.00000 5.00050 5.02563 5.11063 ns 1,2,4
DIF 266
3.66463 3.74963 3.74963 3.75000 3.75038 3.76922 3.85422 ns 1,2,4
DIF 333
2.91470 2.99970 2.99970 3.00000 3.00030 3.01538 3.10038 ns 1,2,4
DIF 400
2.41475 2.49975 2.49975 2.50000 2.50025 2.51282 2.59782 ns 1,2,4
Clock Periods Differential Outputs with Spread Spectrum Disabled
1 Clock 1us 0.1s 0.1s 0.1s 1us 1 Clock
Lg- -SSC -ppm error 0ppm + ppm error +SSC Lg+
Absolute
Period
Short-term
Avera
g
e
Long-Term
Avera
g
e
Period
Long-Term
Avera
g
e
Short-term
Avera
g
e
Period
Minimum
Absolute
Period
Minimum
Absolute
Period
Minimum
Absolute
Period
Nominal Maximum Maximum Maximum
DIF 100
9.87400 9.99900 10.00000 10.00100 10.17630 ns 1,2,3
DIF 133
7.41425 7.49925 7.50000 7.50075 7.62345 ns 1,2,4
DIF 166
5.91440 5.99940 6.00000 6.00060 6.11576 ns 1,2,4
DIF 200
4.91450 4.99950 5.00000 5.00050 5.11063 ns 1,2,4
DIF 266
3.66463 3.74963 3.75000 3.75038 3.85422 ns 1,2,4
DIF 333
2.91470 2.99970 3.00000 3.00030 3.10038 ns 1,2,4
DIF 400
2.41475 2.49975 2.50000 2.50025 2.59782 ns 1,2,4
1
Guaranteed by design and characterization, not 100% tested in production.
3
Driven by SRC output of main clock, PLL or Bypass mode
4
Driven by CPU output of CK410/CK505 main clock,
B
yp
ass mode onl
y
Definition
Units
Signal NameSignal Name
Measurement
Window
Symbol
2
All Long Term Accuracy specifications are guaranteed with the assumption that the input clock complies with
CK409/CK410/CK505 accuracy requirements. The 9DB403/803 itself does not contribute to ppm error.
Notes
Notes
Definition
Measurement
Window
Units
Symbol
IDT
®
Four Output Differential Buffer for PCIe Gen 1 and Gen 2 ICS9DB403D REV R 11/1/12
ICS9DB403D
Four Output Differential Buffer for PCIe for Gen 1 and Gen 2
9
Common Recommendations for Differential Routing Dimension or Value Unit Figure
L1 length, route as non-coupled 50ohm trace 0.5 max inch 1
L2 length, route as non-coupled 50ohm trace 0.2 max inch 1
L3 length, route as non-coupled 50ohm trace 0.2 max inch 1
Rs 33 ohm 1
Rt 49.9 ohm 1
Down Device Differential Routing
L4 length, route as coupled microstrip 100ohm differential trace 2 min to 16 max inch 1
L4 length, route as coupled stripline 100ohm differential trace 1.8 min to 14.4 max inch 1
Differential Routing to PCI Express Connector
L4 length, route as coupled microstrip 100ohm differential trace 0.25 to 14 max inch 2
L4 length, route as coupled stripline 100ohm differential trace 0.225 min to 12.6 max inch 2
SRC Reference Clock
HCSL Output Buffer
L1
L1'
Rs
L2
L2'
Rs
L4'
L4
L3L3'
Rt Rt
PCI Express
Down Device
REF_CLK Input
Figure 1: Down Device Routing
HCSL Output Buffer
L1
L1'
Rs
L2
L2'
Rs
L4'
L4
L3L3'
Rt Rt
PCI Express
Add-in Board
REF_CLK Input
Figure 2: PCI Express Connector Routing
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19

9DB403DGILFT

Mfr. #:
Buy 9DB403DGILFT
Manufacturer:
IDT
Description:
Clock Buffer 4-output Differential Buffer For PCIe Gen1-2
Lifecycle:
New from this manufacturer.
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