RT8202/A/B
13
DS8202/A/B-03 April 2010 www.richtek.com
where V
FB
is 0.75V.
Note that in order for the device to regulate in a controlled
manner, the ripple content at the feedback pin, V
FB
, should
be approximately 15mV at minimum V
BAT
, and worst case
no smaller than 10mV. If V
ripple
at minimum V
BAT
is less
than 15mV, the above component values should be
revisited in order to improve this. Quite often a small
capacitor, C1, is required in parallel with the top feedback
resistor, R1, in order to ensure that V
FB
is large enough.
The value of C1 can be calculated as follows, where R2 is
the bottom feedback resistor.
Firstly calculating the value of Z1 required :
()
ripple_VBAT(MIN)
R2
Z1 = V 0.015
0.015
×−Ω
Secondly calculating the value of C1 required to achieve
this :
(
)
SW_VBAT(MIN)
11
Z1 R1
C1 = F
2f
π
××
Finally using the equation as follows to verify the value of
V
FB
:
FB_VBAT(MIN) ripple_VBAT(MIN)
SW_VBAT(MIN)
V = V
R2
V
1
R2+
1
2f C1
R1
π
⎡⎤
⎢⎥
⎢⎥
×
⎢⎥
⎢⎥
⎢⎥
× ×
⎣⎦
where V
ripple_VBAT(MIN)
is the output ripple voltage in
minimum V
BAT
;
f
sw_VBAT(MIN)
is the switching frequency in minimum V
BAT
;
V
FB_VBAT(MIN)
is the ripple voltage into FB pin in minimum
V
BAT
.
PHASE
BOOT
R1
R2
V
OUT
V
IN
UGATE
VOUT
FB
GND
C1
C2
Z1
Figure 5. Setting The Output Voltage
For application that output voltage is higher than 3.3V,
user can also use a voltage divider to keep VOUT pin
voltage within 0.75V to 2.8V as shown in Figure 6. For
this case, T
ON
can be determined as below :
TON OUT_FB
TON ON
IN
TON OUT_FB
TON ON
IN
RV
If R < 2M then T = 3.85p
V0.5
R V
If R 2M then T = 3.55p
V0.4
×
Ω×
×
≥Ω ×
Where R
TON
is T
ON
set resistor and the V
OUT_FB
is the
output signal of resistor divider. Since the switching
frequency is
OUT
S
IN ON
V
F =
VT×
For a given switching frequency, we can obtain the R
TON
as below
TON
OUT OUT
TON
IN OUT_FB S
TON
OUT OUT
TON
IN OUT_FB S
If R < 2M then
V0.5V
1
R =
V V F 3.85p
If R 2M then
V0.4V
1
R =
V V F 3.55p
Ω
××
×
≥Ω
××
×
Figure 6. Output Voltage Setting for V
OUT
> 3.3V
Application
Output Voltage Setting (FB)
The output voltage can be adjusted from 0.75V to 3.3V by
setting the feedback resistor R1 and R2 (Figure 5). Choose
R2 to be approximately 10kΩ, and solve for R1 using the
equation:
PHASE
BOOT
R1
R2
V
OUT
V
IN
UGATE
VOUT
FB
GND
C2
VIN
R
TON
R3
R4
V
OUT_FB
OUT FB
R1
V = V 1
R2
⎡⎤
⎛⎞
×+
⎜⎟
⎢⎥
⎝⎠
⎣⎦
RT8202/A/B
14
DS8202/A/B-03 April 2010www.richtek.com
Do not put high value ceramic capacitors directly across
the outputs without taking precautions to ensure stability.
Large ceramic capacitors can have a high ESR zero
frequency and cause erratic and unstable operation.
However, it is easy to add sufficient series resistance by
placing the capacitors a couple of inches downstream from
the inductor and connecting V
OUT
or FB divider close to
the inductor.
There are two related but distinct ways including double
pulsing and feedback loop instability to identify the
unstable operation.
Double-pulsing occurs due to noise on the output or
because the ESR is too low that there is not enough
voltage ramp in the output voltage signal. The fools the
error comparator into triggering a new cycle immediately
after 400ns minimum off-time period has expired. Double-
pulsing is more annoying than harmful, resulting in nothing
worse than increased output ripple. However, it may
indicate the possible presence of loop instability, which
is caused by insufficient ESR.
Loop instability can result in oscillation at the output after
line or load perturbations that can trip the over voltage
protection latch or cause the output voltage to fall below
the tolerance limit.
The easiest method for stability checking is to apply a
very zero-to-max load transient and carefully observe the
output-voltage-ripple envelope for overshoot and ringing. It
helps to simultaneously monitor the inductor current with
AC probe. Do not allow more than one ringing cycle after
the initial step-response under- or over-shoot.
Thermal Considerations
For continuous operation, do not exceed absolute
maximum operation junction temperature.
The maximum power dissipation depends on the thermal
resistance of IC package, PCB layout, the rate of
surroundings airflow and temperature difference between
junction to ambient. The maximum power dissipation can
be calculated by following formula :
P
D(MAX)
= ( T
J(MAX)
- T
A
) / θ
JA
Where T
J(MAX)
is the maximum operation junction
temperature 125°C, T
A
is the ambient temperature and the
θ
JA
is the junction to ambient thermal resistance.
Output Inductor Selection
The switching frequency (on-time) and operating point (%
ripple or L
IR
) determine the inductor value as follows :
ON IN OUT
IR LOAD(MAX)
T(V - V)
L =
LI
×
×
Find a low pass inductor having the lowest possible DC
resistance that fits in the allowed dimensions. Ferrite cores
are often the best choice, although powdered iron is
inexpensive and can work well at 200kHz. The core must
be large enough and not to saturate at the peak inductor
current (I
PEAK
) :
I
PEAK
= I
LOAD(MAX)
+ [(L
IR
/ 2) x I
LOAD(MAX)
]
Output Capacitor Selection
The output filter capacitor must have ESR low enough to
meet output ripple and load transient requirement, yet have
high enough ESR to satisfy stability requirements. Also,
the capacitance value must be high enough to absorb the
inductor energy going from a full load to no load condition
without tripping the OVP circuit.
For CPU core voltage converters and other applications
where the output is subject to violent load transient, the
output capacitor's size depends on how much ESR is
needed to prevent the output from dipping too low under a
load transient. Ignoring the sag due to finite capacitance :
P-P
IR LOAD(MAX)
V
ESR
LI
×
P-P
LOAD(MAX)
V
ESR
I
In non-CPU applications, the output capacitor's size
depends on how much ESR is needed to maintain at an
acceptable level of output voltage ripple :
Organic semiconductor capacitor(s) or specially polymer
capacitor(s) are recommended.
Output Capacitor Stability
Stability is determined by the value of the ESR zero relative
to the switching frequency. The point of instability is given
by the following equation :
SW
ESR
OUT
f
1
f =
2 ESR C 4
π
×× ×
RT8202/A/B
15
DS8202/A/B-03 April 2010 www.richtek.com
For recommended operating conditions specification of
RT8202/A/B, where T
J(MAX)
is the maximum junction
temperature of the die (125°C) and T
A
is the maximum
ambient temperature. The junction to ambient thermal
resistance θ
JA
is layout dependent. For WQFN-16L 3x3
packages, the thermal resistance θ
JA
is 68°C/W on the
standard JEDEC 51-7 four layers thermal test board. For
WQFN-14L 3.5x3.5 package, the thermal resistance θ
JA
is 60°C/W on the standard JEDEC 51-7 four layers thermal
test board.
The maximum power dissipation at T
A
= 25°C
can be calculated by following formula :
P
D(MAX)
= (125°C 2°C) / (68°C/W) = 1.471W for
WQFN-16L 3x3 packages
P
D(MAX)
= (125°C 25°C) / (54°C/W) = 1.852W for
WQFN-16L 4x4 packages
P
D(MAX)
= (125°C 25°C) / (60°C/W) = 1.667W for
WQFN-14L 3.5x3.5 packages
The maximum power dissipation depends on operating
ambient temperature for fixed T
J(MAX)
and thermal
resistance θ
JA
. For RT8202/A/B packages, the Figure 7
of derating curves allows the designer to see the effect of
rising ambient temperature on the maximum power
allowed.
Figure 7. Derating Curves for RT8202/A/B Packages
Layout Considerations
Layout is very important in high frequency switching
converter design. If designed improperly, the PCB could
radiate excessive noise and contribute to the converter
instability. Certain points must be considered before
starting a layout for RT8202/A/B.
` Connect RC low pass filter from VDDP to VDD, 1uF and
10Ω are recommended. Place the filter capacitor close
to the IC.
` Keep current limit setting network as close as possible
to the IC. Routing of the network should avoid coupling
to high voltage switching node.
` Connections from the drivers to the respective gate of
the high side or the low side MOSFET should be as
short as possible to reduce stray inductance.
` All sensitive analog traces and components such as
VOUT, FB, GND, EN/DEM, PGOOD, OC, VDD, and
TON should be placed away from high voltage switching
nodes such as PHASE, LGATE, UGATE, or BOOT
nodes to avoid coupling. Use internal layer(s) as ground
plane(s) and shield the feedback trace from power traces
and components.
` Current sense connections must always be made using
Kelvin connections to ensure an accurate signal, with
the current limit resistor located at the device.
` Power sections should connect directly to ground
plane(s) using multiple vias as required for current
handling (including the chip power ground connections).
Power components should be placed to minimize loops
and reduce losses.
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
0 25 50 75 100 125
Ambient Temperature (°C)
Maximum Power Dissipation (W)
WQFN -16L 4x4
Four Layer PCB
WQFN -16L 3x3
WQFN -14L 3.5x3.5

RT8202AGQW

Mfr. #:
Manufacturer:
Description:
IC REG CTRLR BUCK 16WQFN
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New from this manufacturer.
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