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CY7C197N-25PXC

P1-P3P4-P6P7-P9P10-P12P13-P13
CY7C197N
256 K × 1 Static RAM
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 001-06495 Rev. *D Revised July 1, 2011
256 K × 1 Static RAM
Features
■ High speed
❐ 25 ns
■ CMOS for optimum speed/power
■ Low active power
❐ 880 mW
■ Low standby power
❐ 220 mW
■ Transistor-transistor logic (TTL)-compatible inputs and outputs
■ Automatic power-down when deselected
Functional Description
The CY7C197N is a high-performance CMOS static RAM
organized as 256 K words by 1 bit. Easy memory expansion is
provided by an active LOW Chip Enable (CE) and three-state
drivers. The CY7C197N has an automatic power-down feature,
reducing the power consumption by 75% when deselected.
Writing to the device is accomplished when the Chip Enable (CE
)
and Write Enable (WE
) inputs are both LOW. Data on the input
pin (D
IN
) is written into the memory location specified on the
address pins (A
0
through A
17
).
Reading the device is accomplished by taking chip enable (CE
)
LOW while Write Enable (WE
) remains HIGH. Under these
conditions the contents of the memory location specified on the
address pins will appear on the data output (D
OUT
) pin.
The output pin stays in a high-impedance state when Chip
Enable (CE
) is HIGH or Write Enable (WE) is LOW.
The CY7C197N uses a die coat to insure alpha immunity.
1024 x 256
ARRAY
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
COLUMN
DECODER
ROW DECODER
SENSE AMPS
POWER
DOWN
WE
CE
INPUT BUFFER
DO
DI
A
0
A
9
A
10
A
11
A
12
A
17
A
16
A
15
A
14
A
13
Logic Block Diagram
CY7C197N
Document #: 001-06495 Rev. *D Page 2 of 13
Contents
Pin Configurations ...........................................................3
Selection Guide ................................................................3
Maximum Ratings .............................................................4
Operating Range ...............................................................4
Electrical Characteristics .................................................4
Capacitance ......................................................................4
Switching Characteristics ................................................5
Switching Waveforms ......................................................6
Typical DC and AC Characteristics ................................8
CY7C197N Truth Table .....................................................9
Ordering Information ........................................................9
Ordering Code Definitions ...........................................9
Package Diagram ............................................................10
Acronyms ........................................................................11
Document Conventions .................................................11
Units of Measure .......................................................11
Document History Page .................................................12
Sales, Solutions, and Legal Information ......................13
Worldwide Sales and Design Support ....................... 13
Products ....................................................................13
PSoC Solutions .........................................................13
CY7C197N
Document #: 001-06495 Rev. *D Page 3 of 13
Pin Configurations
Figure 1. 24-pin DIP (Top View)
WE
GND
1
2
3
4
5
6
7
8
9
10
11
14
15
16
20
19
18
17
21
24
23
22
7C197
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
CE
V
CC
A
17
A
16
A
15
A
14
A
11
A
10
A
9
D
IN
A
13
A
12
D
OUT
12 13
Selection Guide
Description -25
Maximum access time (ns) 25
Maximum operating current (mA) 95
Maximum standby current (mA) 30
P1-P3P4-P6P7-P9P10-P12P13-P13

CY7C197N-25PXC

Mfr. #:
Buy CY7C197N-25PXC
Manufacturer:
Cypress Semiconductor
Description:
SRAM 256Kx1 SEP IO SRAM
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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