CY7C197N-25PXC Datasheet CY7C197N-25PXC | P4-P6

CY7C197N

Document #: 001-06495 Rev. *D Page 4 of 13

Maximum Ratings

Exceeding maximum ratings may impair the useful life of the

device. These user guidelines are not tested.

Storage temperature ................................ –65 °C to +150 °C

Ambient temperature with

power applied ........................................... –55 °C to +125 °C

Supply voltage to ground potential

(Pin 24 to Pin 12)..........................................–0.5 V to +7.0 V

DC voltage applied to outputs

in High Z state

[1]

..................................–0.5 V to V

+ 0.5 V

DC input voltage

[1]

...............................–0.5 V to V

+ 0.5 V

Output current into outputs (LOW) ..............................20 mA

Static discharge voltage.......................................... > 2001 V

(per MIL-STD-883, Method 3015)

Latch up current..................................................... > 200 mA

Operating Range

Range Ambient Temperature V

Commercial 0°C to +70°C 5 V ± 10%

Electrical Characteristics

Over the Operating Range

Parameter Description Test Conditions

-25

Unit

Min Max

Output HIGH voltage V

= Min, I

= –4.0 mA 2.4 – V

Output LOW voltage V

= Min, I

=12.0 mA – 0.4 V

Input HIGH voltage 2.2 V

+ 0.3 V V

Input LOW voltage

[1]

–0.5 0.8 V

Input load current GND < V

< V

–5 +5 A

Output leakage current GND < V

< V

, Output Disabled –5 +5 A

Output short circuit current

[2]

= Max, V

OUT

= GND – –300 mA

operating supply current V

= Max, I

OUT

= 0 mA, f = f

MAX

= 1/t

– 95 mA

SB1

Automatic CE power-down

current—TTL inputs

[3]

Max V

, CE > V

, V

> V

< V

, f = f

MAX

– 30 mA

SB2

Automatic CE power-down

current—CMOS inputs

[3]

Max V

, CE > V

– 0.3 V,

> V

– 0.3 V or V

< 0.3 V

–

15 mA

Capacitance

[4]

Parameter Description Test Conditions Max Unit

Input capacitance T

= 25 °C, f = 1 MHz, V

= 5.0 V 8 pF

OUT

Output capacitance 10 pF

Notes

1. V

(min.)

= -2.0 V for pulse durations of less than 20 ns.

2. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.

3. A pull-up resistor to V

on the CE input is required to keep the device deselected during V

power-up, otherwise I

will exceed values given.

4. Tested initially and after any design or process changes that may affect these parameters.

CY7C197N

Document #: 001-06495 Rev. *D Page 5 of 13

Figure 2. AC Test Loads and Waveforms

[5]

Switching Characteristics

Over the Operating Range

[6]

Parameter Description

-25

Unit

Min Max

READ CYCLE

Read cycle time 25 – ns

Address to data valid – 25 ns

OHA

Output hold from address change 3 – ns

ACE

CE LOW to data valid – 25 ns

LZCE

CE LOW to low Z

[7]

3 – ns

HZCE

CE HIGH to high Z

[7, 8]

0 11 ns

CE LOW to power-up 0 – ns

CE HIGH to power-down – 20 ns

WRITE CYCLE

[9]

Write cycle time 25 – ns

SCE

CE LOW to write end 20 – ns

Address setup to write end 20 – ns

Address hold from write end 0 – ns

Address setup to write start 0 – ns

PWE

WE pulse width 20 – ns

Data setup to write end 15 – ns

Data hold from write end 0 – ns

LZWE

WE HIGH to low Z

[7]

3 – ns

HZWE

WE LOW to high Z

[7, 8]

0 11 ns

255 

(255 MIL)

R1 329 

3.0 V

5 V

OUTPUT

R1 329

202 

(255 MIL)

30 pF

INCLUDING

JIG AND

SCOPE

GND

90%

10%

90%

10%

5 V

OUTPUT

5pF

INCLUDING

JIG AND

SCOPE

(a) (b)

OUTPUT 1.90 V

Equivalent to: THÉ VENIN EQUIVALENT

Commercial

ALL INPUT PULSES

125 

Notes

5. t

= < 5 ns for the -25 and slower speeds.

6. Test conditions assume signal transition time of 5 ns or less for -25 and slower speeds, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V, and output

loading of the specified I

and 30-pF load capacitance.

7. At any given temperature and voltage condition, t

HZCE

is less than t

LZCE

and t

HZWE

is less than t

LZWE

for any given device.

8. t

HZCE

and t

HZWE

are specified with C

= 5 pF as in part (b) in AC Test Loads and Waveforms. Transition is measured ±500 mV from steady-state voltage.

9. The internal write time of the memory is defined by the overlap of CE

LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate

a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.

CY7C197N

Document #: 001-06495 Rev. *D Page 6 of 13

Switching Waveforms

Figure 3. Read Cycle No. 1

[10, 11]

Figure 4. Read Cycle No. 2

[10]

Figure 5. Write Cycle No. 1 (WE Controlled)

[12]

ADDRESS

DATA OUT PREVIOUS DATA VALID

DATA VALID

OHA

50%

DATA VALID

ACE

LZCE

DATA OUT

HIGH IMPEDANCE

IMPEDANCE

ICC

ISB

HZCE

HIGH

SUPPLY

CURRENT

DATA VALID

DATA UNDEFINED

HIGH IMPEDANCE

SCE

PWE

HZWE

LZWE

DATA IN

DATA OUT

ADDRESS

C197-8

Notes

10. WE

is HIGH for read cycle.

11. Device is continuously selected, CE

= V

12. If CE

goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P13

CY7C197N-25PXC

Mfr. #:

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Manufacturer:

Cypress Semiconductor

Description:

SRAM 256Kx1 SEP IO SRAM

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CY7C197N-25PXC