6.42
IDT7015S/L
High-Speed 8K x 9 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
13
2954 drw 13
t
DW
t
APS
ADDR
"A"
t
WC
DATA
OUT "B"
MATCH
t
WP
R/W
"A"
DATA
IN "A"
ADDR
"B"
t
DH
VALID
(1)
MATCH
BUSY
"B"
t
BDA
VALID
t
BDD
t
DDD
(3)
t
WDD
Timing Waveform of Read with BUSY
(2,4,5)
(M/S = VIH)
Timing Waveform of Write with BUSY
(3)
NOTES:
1. tWH must be met for both BUSY input (SLAVE) and output (MASTER).
2. BUSY is asserted on port "B" blocking R/W"B", until BUSY"B" goes HIGH.
3. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from Port "A".
NOTES:
1. To ensure that the earlier of the two ports wins. tAPS is ignored for M/S=VIL
2. CEL = CER = VIL
3. OE = VIL for the reading port.
4. If M/S=VIL (SLAVE), BUSY is an input. Then for this example, BUSY“A”=VIH and BUSY“B” input is shown above.
5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from Port "A".
2954 drw 14
R/W
"A"
BUSY
"B"
t
WP
t
WB
R/W
"B"
t
WH
(1)
(2)
