6.42
IDT7015S/L
High-Speed 8K x 9 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
7
NOTES:
1. Transition is measured 0mV from Low- or High-impedance voltage with load (Figures 1 and 2).
2. This parameter is guaranteed by device characterization but not tested.
3. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL.
4. 'X' in part numbers indicates power rating (S or L).
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range
(4)
7015X12
Com'l Only
7015X15
Com'l Only
7015X17
Com'l Only
UnitSymbol Parameter Min.Max.Min.Max.Min.Max.
READ CYCLE
t
RC Read Cycle Time 12
____
15
____
17
____
ns
t
AA Address Access Time
____
12
____
15
____
17 ns
t
ACE Chip Enable Access Time
(3)
____
12
____
15
____
17 ns
t
AOE Output Enable Access Time
____
8
____
10
____
10 ns
t
OH Output Hold from Address Change 3
____
3
____
3
____
ns
t
LZ Output Low-Z Time
(1,2)
3
____
3
____
3
____
ns
t
HZ Output High-Z Time
(1,2)
____
10
____
10
____
10 ns
t
PU Chip Enable to Power Up Time
(2)
0
____
0
____
0
____
ns
t
PD Chip Disable to Power Down Time
(2)
____
12
____
15
____
17 ns
t
SOP Semaphore Flag Update Pulse (OE or SEM)10
____
10
____
10
____
ns
t
SAA Semaphore Address Access Time
____
12
____
15
____
17 ns
2954 tbl 12a
7015X20
Com'l & Ind
7015X25
Com'l Only
7015X35
Com'l Only
UnitSymbol Parameter Min. Max. Min. Max. Min. Max.
READ CYCLE
t
RC
Read Cycle Time 20
____
25
____
35
____
ns
t
AA
Address Access Time
____
20
____
25
____
35 ns
t
ACE
Chip Enable Access Time
(3)
____
20
____
25
____
35 ns
t
AOE
Output Enable Access Time
____
12
____
13
____
20 ns
t
OH
Output Hold from Address Change 3
____
3
____
3
____
ns
t
LZ
Output Low-Z Time
(1,2)
3
____
3
____
3
____
ns
t
HZ
Output High-Z Time
(1,2)
____
12
____
15
____
20 ns
t
PU
Chip Enable to Power Up Time
(2)
0
____
0
____
0
____
ns
t
PD
Chip Disable to Power Down Time
(2)
____
20
____
25
____
35 ns
t
SOP
Semaphore Flag Update Pulse (OE or SEM)10
____
10
____
15
____
ns
t
SAA
Semaphore Address Access Time
____
20
____
25
____
35 ns
2954 tbl 12b
6.42
IDT7015S/L
High-Speed 8K x 9 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
8
Waveform of Read Cycles
(5)
NOTES:
1. Timing depends on which signal is asserted last, OE or CE.
2. Timing depends on which signal is de-asserted first, CE or OE.
3. tBDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY
has no relation to valid output data.
4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA or tBDD.
5. SEM = VIH.
Timing of Power-Up / Power-Down
tRC
R/W
CE
ADDR
tAA
OE
2954 drw 07
(4)
tACE
(4)
tAOE
(4)
(1)
tLZ
tOH
(2)
tHZ
(3,4)
tBDD
DATAOUT
BUSY
OUT
VALID DATA
(4)
CE
2954 drw 08
t
PU
I
CC
I
SB
t
PD
50%
50%
,
6.42
IDT7015S/L
High-Speed 8K x 9 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
9
NOTES:
1. Transition is measured 0mV from Low- or High-impedance voltage with the Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization but not tested.
3. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW time.
4. The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary over voltage
and temperature, the actual tDH will always be smaller than the actual tOW.
5. 'X' in part numbers indicates power rating (S or L).
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage
(5)
Symbol Parameter
7015X12
Com'l Only
7015X15
Com'l Only
7015X17
Com'l Only
UnitMin. Max. Min. Max. Min. Max.
WRITE CYCLE
t
WC
Write Cycle Time 12
____
15
____
17
____
ns
t
EW
Chip Enable to End-of-Write
(3)
10
____
12
____
12
____
ns
t
AW
Address Valid to End-of-Write 10
____
12
____
12
____
ns
t
AS
Address Set-up Time
(3)
0
____
0
____
0
____
ns
t
WP
Write Pulse Width 10
____
12
____
12
____
ns
t
WR
Write Recovery Time 2
____
2
____
0
____
ns
t
DW
Data Valid to End-of-Write 10
____
10
____
10
____
ns
t
HZ
Output High-Z Time
(1,2)
____
10
____
10
____
10 ns
t
DH
Data Hold Time
(4)
0
____
0
____
0
____
ns
t
WZ
Write Enable to Output in High-Z
(1,2)
____
10
____
10
____
10 ns
t
OW
Output Active from End-of-Write
(1, 2 ,4)
3
____
3
____
0
____
ns
t
SWRD
SEM Flag Write to Read Time
5
____
5
____
5
____
ns
t
SPS
SEM Flag Contention Window
5
____
5
____
5
____
ns
2954 tbl 13a
Symbol Parameter
7015X20
Com'l & Ind
7015X25
Com'l Only
7015X35
Com'l Only
UnitMin. Max. Min. Max. Min. Max.
WRITE CYCLE
t
WC
Write Cycle Time 20
____
25
____
35
____
ns
t
EW
Chip Enable to End-of-Write
(3)
15
____
20
____
30
____
ns
t
AW
Address Valid to End-of-Write 15
____
20
____
30
____
ns
t
AS
Address Set-up Time
(3)
0
____
0
____
0
____
ns
t
WP
Write Pulse Width 15
____
20
____
25
____
ns
t
WR
Write Recovery Time 2
____
2
____
0
____
ns
t
DW
Data Valid to End-of-Write 15
____
15
____
15
____
ns
t
HZ
Output High-Z Time
(1,2)
____
12
____
15
____
20 ns
t
DH
Data Hold Time
(4)
0
____
0
____
0
____
ns
t
WZ
Write Enable to Output in High-Z
(1,2)
____
12
____
15
____
20 ns
t
OW
Output Active from End-of-Write
(1,2,4)
3
____
3
____
3
____
ns
t
SWRD
SEM Flag Write to Read Time
5
____
5
____
5
____
ns
t
SPS
SEM Flag Contention Window
5
____
5
____
5
____
ns
2954 tbl 13b

7015S35J

Mfr. #:
Manufacturer:
IDT
Description:
SRAM 8KX8 DUAL PORT BUSY/INT
Lifecycle:
New from this manufacturer.
Delivery:
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Payment:
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