NB2308AI2HDTG

Semiconductor Components Industries, LLC, 2010
October, 2010 -- Rev. 8
1 Publication Order Number:
NB2308A/D
NB2308A
3.3 V Zero Delay
Clock Buffer
The NB2308A is a versatile, 3.3 V zero delay buffer designed to
distribute high--speed clocks. It is available in a 16 pin package. The
part has an on--chip PLL which locks to an input clock presented on
the REF pin. The PLL feedback is required to be driven to FBK pin,
and can be obtained from one of the outputs. The input--to--output
propagation delay is guaranteed to be less than 250 ps, and the
output--to--output skew is guaranteed to be less than 200 ps.
The NB2308A has two banks of four outputs each, which can be
controlled by the select inputs as shown in the Select Input Decoding
Table. If all the output clocks are not required, Bank B can be
three--stated. The select input also allows the input clock to be directly
applied to the outputs for chip and system testing purposes.
Multiple NB2308A devices can accept the same input clock and
distribute it. In this case the skew between the outputs of the two
devices is guaranteed to be less than 700 ps.
The NB2308A is available in five different configurations (Refer to
NB2308A Configurations Table). The NB2308AI1 is the base part,
where the output frequencies equal the reference if there is no counter
in the feedback path. The NB2308AI1H is the high--drive version of
the --1 and the rise and fall times on this device are much faster.
The NB2308AI2 allows the user to obtain 2X and 1X frequencies on
each output bank. The exact configuration and output frequencies
depends on which output drives the feedback pin. The NB2308AI3
allows the user to obtain 4X and 2X frequencies on the outputs.
The NB2308AI4 enables the user to obtain 2X clocks on all outputs.
Thus, the part is extremely versatile, and can be used in a variety of
applications.
The NB2308AI5H is a high--drive version with REF/2 on both
banks.
Features
Zero Input -- Output Propagation Delay, Adjustable by Capacitive
Load on FBK Input
Multiple Configurations -- Refer to NB2308A Configurations Table
Input Frequency Range: 15 MHz to 133 MHz
Multiple Low--Skew Outputs
Output--Output Skew Less than 200 ps
Device--Device Skew Less than 700 ps
Two banks of four outputs, three--stateable by two select inputs
Less than 200 ps Cycle--to--Cycle Jitter
Available in 16--pin SOIC and TSSOP Packages
3.3 V Operation
Guaranteed Across Commercial and Industrial Temperature Ranges
Advanced 0.35 m CMOS Technology
These are Pb--Free Devices
MARKING
DIAGRAMS*
XXXX = Device Code
A = Assembly Location
WL, L = Wafer Lot
Y = Year
WW, W = Work Week
GorG = Pb--Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
See detailedordering and shipping information inthe package
dimensions section on page 9 of this data sheet.
ORDERING INFORMATION
http://onsemi.com
SOIC--16
D SUFFIX
CASE 751B
1
16
1
16
1
16
1
16
XXXX
XXXX
ALYWG
G
XXXXXXXXXG
AWL YWW
TSSOP--16
DT SUFFIX
CASE 948F
NB2308A
http://onsemi.com
2
FBK
CLKA1
CLKA2
CLKA3
CLKA4
PLL
MUX
CLKB1
CLKB2
CLKB3
CLKB4
SELECT INPUT
DECODING
Figure 1. Block Diagram
(see Figures 11, 12, 13, 14 and 15 for device specific Block Diagrams)
REF
S2
S1
Extra Divider (--2, --3)
Extra Divider (--5H)
Extra Divider (--3, --4)
÷2
÷2
÷2
Table 1. CONFIGURATIONS
Device Feedback From Bank A Frequency Bank B Frequency
NB2308AI1 Bank A or Bank B Reference Reference
NB2308AI1H Bank A or Bank B Reference Reference
NB2308AI2 Bank A Reference Reference ÷2
NB2308AI2 Bank B 2 X Reference Reference
NB2308AI3 Bank A 2 X Reference Reference or Reference (Note 1)
NB2308AI3 Bank B 4 X Reference 2 X Reference
NB2308AI4 Bank A or Bank B 2 X Reference 2 X Reference
NB2308AI5H Bank A or Bank B Reference ÷2 Reference ÷2
1. Output phase is indeterminant (0 or 180 from input clock). If phase integrity is required, use the NB2308AI2.
Table 2. SELECT INPUT DECODING
S2 S1 Clock A1 -- A4 Clock B1 -- B4 Output Source PLL ShutDown
0 0 Three--state Three--state PLL Y
0 1 Driven Three--state PLL N
1 0 Driven (Note 2) Driven Reference Y
1 1 Driven Driven PLL N
2. Outputs inverted on 2308--2 and 2308--3 in bypass m ode, S2 = 1 and S1 = 0.
NB2308A
http://onsemi.com
3
Figure 2. Pin Configuration
V
DD
1
2
3
4
16
15
14
13
REF
CLKA1
CLKA2
GND
FBK
CLKA4
CLKA3
NB2308A
V
DD
5
6
7
8
12
11
10
9
CLKB1
CLKB2
S2
CLKB4
CLKB3
S1
GND
Table 3. PIN DESCRIPTION
Pin # Pin Name Description
1 REF (Note 3) Input reference frequency, 5 V tolerant input.
2 CLKA1 (Note 4) Buffered clock output, Bank A.
3 CLKA2 (Note 4) Buffered clock output, Bank A.
4 V
DD
3.3 V supply.
5 GND Ground.
6 CLKB1 (Note 4) Buffered clock output, Bank B.
7 CLKB2 (Note 4) Buffered clock output, Bank B.
8 S2 (Note 5) Select input, bit 2.
9 S1 (Note 5) Select input, bit 1.
10 CLKB3 (Note 4) Buffered clock output, Bank B.
11 CLKB4 (Note 4) Buffered clock output, Bank B.
12 GND Ground.
13 V
DD
3.3 V supply.
14 CLKA3 (Note 4) Buffered clock output, Bank A.
15 CLKA4 (Note 4) Buffered clock output, Bank A.
16 FBK PLL feedback input.
3. Weak pulldown.
4. Weak pulldown on all outputs.
5. Weak pullup on these inputs.

NB2308AI2HDTG

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Phase Locked Loops - PLL HF-ZERO DELAY BUFFER
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union