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NB2308AI2HDTG

P1-P3P4-P6P7-P9P10-P12
NB2308A
http://onsemi.com
4
Table 4. MAXIMUM RATINGS
Parameter Min Max Unit
Supply Voltage to Ground Potential -- 0 . 5 +7.0 V
DC Input Voltage (Except REF) -- 0 . 5 V
DD
+0.5 V
DC Input Voltage (REF) -- 0 . 5 7 V
Storage Temperature -- 6 5 +150 C
Maximum Soldering Temperature (10 sec) 260 C
Junction Temperature 150 C
Static Discharge Voltage (per MIL--STD--883, Method 3015) >2000 V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
Table 5. OPERATING CONDITIONS
Parameter Description Min Max Unit
V
DD
Supply Voltage 3.0 3.6 V
T
A
Operating Temperature (Ambient Temperature) Industrial
Commercial
-- 4 0
0
85
70
C
C
L
Load Capacitance, below 100 MHz 30 pF
C
L
Load Capacitance, from 100 MHz to 133 MHz 15 pF
C
IN
Input Capacitance (Note 6) 7 pF
6. Applies to both REF Clock and FBK.
Table 6. ELECTRICAL CHARACTERISTICS V
CC
= 3.0 V to 3.6 V, GND = 0 V, T
A
=--40Cto+85C
Parameter
Description Test Conditions Min Max Unit
V
IL
Input LOW Voltage 0.8 V
V
IH
Input HIGH Voltage 2.0 V
I
IL
Input LOW Current V
IN
=0V 50.0
mA
I
IH
Input HIGH Current V
IN
=V
DD
100.0
mA
V
OL
Output LOW Voltage I
OL
= 8 mA (--1, --2, --3, --4)
I
OL
=12mA(--1H,--5H)
0.4 V
V
OH
Output HIGH Voltage I
OH
= --8 mA (--1, --2, --3, --4)
I
OH
= --12 mA (--1H, --5H)
2.4 V
I
DD
Supply Current (Note 7)
Unloaded outputs 100 MHz REF -- 2 , -- 3 , -- 4 49 mA
Select inputs at V
DD
or GND -- 1 H , -- 5 H 60 mA
Unloaded outputs, 66 MHz REF
(--1, --2, --3, --4)
34 mA
Unloaded outputs, 33 MHz REF
(--1, --2, --3, --4)
18 mA
7. Supply currents are measured for PLL--Bypass Mode (S2 = 1, S1 = 0).
NB2308A
http://onsemi.com
5
Table 7. SWITCHING CHARACTERISTICS V
CC
= 3.0 V to 3.6 V, GND = 0 V, T
A
=--40Cto+85C
Parameter
Description Test Conditions Min Typ Max Unit
t
1
Output Frequency 30 pF load (all devices)
15 pF load (--1H, --5H)
15 pF load (--1, --2, --3, --4)
15
15
15
100
133.3
133.3
MHz
t
1
Duty Cycle = (t
2
/t
1
) * 100
(all devices)
Measured at 1.4 V, F
OUT
= < 66.66 MHz
30 pF load
40.0 50.0 60.0
%
Measured at 1.4 V, F
OUT
=<50MHz
15 pF load
45.0 50.0 55.0
t
3
Output Rise Time
(--1, --2, --3, --4)
Measured between 0.8 V and 2.0 V
30 pF load
2.20
ns
Measured between 0.8 V and 2.0 V
15 pF load
1.50
Output Rise Time
(-- 1H, --5H)
Measured between 0.8 V and 2.0 V
30 pF load
1.50
t
4
Output Fall Time
(--1, --2, --3, --4)
Measured between 2.0 V and 0.8 V
30 pF load
2.20
ns
Measured between 0.8 V and 2.0 V
15 pF load
1.50
Output Fall Time
(-- 1H, --5H)
Measured between 2.0 V and 0.8 V
30 pF load
1.25
t
5
Output--to--Output Skew on same Bank
(--1, --2, --3, --4)
All outputs equally loaded 200
ps
Output--to--Output Skew
(-- 1H, --5H)
All outputs equally loaded 200
Output Bank A--to--Output Bank B Skew
(--1, --4, --5H)
All outputs equally loaded 200
Output Bank A--to--Output Bank B Skew
(--2, --3)
All outputs equally loaded 400
t
6
Delay, REF Rising Edge to FBK
Rising Edge
Measured at V
DD
/2 0 250 ps
t
7
Device--to--Device Skew Measured at V
DD
/2 on the FBK pins of the
device
0 700 ps
t
J
Cycle--to--Cycle Jitter
(--1, --1H, --4, --5H)
Measured at 66.67 MHz, loaded outputs,
15 pF load
200
ps
Measured at 66.67 MHz, loaded outputs,
30 pF load
200
Measured at 133.3 M Hz, loaded outputs
15 pF load
100
Cycle--to--Cycle Jitter
(--2, --3)
Measured at 66.67 MHz, loaded outputs,
30 pF load
400
Measured at 66.67 MHz, loaded outputs,
15 pF load
400
t
LOCK
PLL Lock Time Stable power supply, valid clock presented
on REF and FBK p ins
1.0 ms
NB2308A
http://onsemi.com
6
Zero Delay and Skew Control
All outputs should be uniformly loaded to achieve Zero
Delay between input and output.
Figure 3. REF Input to CLKA/CLKB Delay vs.
Difference in Loading between FBK Pin and
CLKA/CLKB Pins
1500
1000
500
0
--500
--1000
--1500
-- 3 0 -- 2 5 -- 2 0 -- 1 5 -- 1 0 -- 5 0 5 1 0 1 5 2 0 2 5 3 0
REF INPUT TO CLKA/CLKB DELA
Y
(ps)
OUTPUT LOAD DIFFERENCE: FBK LOAD -- CLKA/CLKB LOAD (pF)
To close the feedback loop of the NB2308A, the FBK pin
can be driven from any of the eight available output pins.
The output driving the FBK pin will be driving a total load
of 7 pF plus any additional load that it drives. The relative
loading of this output (with respect to the remaining outputs)
can adjust the input--output delay. This is shown in Figure 3.
For applications requiring zero input--output delay, all
outputs including the one providing feedback should be
equally loaded. If input--output delay adjustments are
required, use the above graph to calculate loading
differences between the feedback output and remaining
outputs. For zero output--output skew, be sure to load
outputs equally.
SWITCHING WAVEFORMS
Figure 4. Duty Cycle Timing
1.4 V 1.4 V 1.4 V
t
1
t
2
Figure 5. All Outputs Rise/Fall Time
t
3
OUTPUT
2.0 V
0.8 V
t
4
2.0 V
0.8 V
3.3 V
0V
1.4 V
1.4 V
t
5
Figure 6. Output -- Output Skew
OUTPUT
OUTPUT
t
6
INPUT
OUTPUT
Figure 7. Input -- Output Propagation Delay
V
DD
2
V
DD
2
Figure 8. Device -- Device Skew
t
7
FBK_Device 1
V
DD
2
V
DD
2
FBK_Device 2
P1-P3P4-P6P7-P9P10-P12

NB2308AI2HDTG

Mfr. #:
Buy NB2308AI2HDTG
Manufacturer:
ON Semiconductor
Description:
Phase Locked Loops - PLL HF-ZERO DELAY BUFFER
Lifecycle:
New from this manufacturer.
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