Data Sheet ADM3054
Rev. D | Page 15 of 20
THEORY OF OPERATION
CAN TRANSCEIVER OPERATION
A CAN bus has two states: dominant and recessive. A dominant
state is present on the bus when the differential voltage between
CANH and CANL is greater than 0.9 V. A recessive state is present
on the bus when the differential voltage between CANH and
CANL is less than 0.5 V. During a dominant bus state, the CANH
pin is high and the CANL pin is low. During a recessive bus
state, both the CANH and CANL pins are in the high imped-
ance state.
The driver drives CANH high and CANL low (dominant state)
when a logic low is present on TxD. If a logic high is present on
TxD, the driver outputs are placed in a high impedance state
(recessive state). The driver output states are presented in Table 9.
The receiver output is low when the bus is in the dominant state
and high when the bus is in the recessive state. If the differential
voltage between CANH and CANL is between 0.5 V and 0.9 V,
the bus state is indeterminate and the receiver output can be
either high or low. The receiver output states for given inputs
are listed in Table 10.
THERMAL SHUTDOWN
The ADM3054 contains thermal shutdown circuitry that protects
the part from excessive power dissipation during fault conditions.
Shorting the driver outputs to a low impedance source can result
in high driver currents. The thermal sensing circuitry detects
the increase in die temperature under this condition and disables
the driver outputs. This circuitry is designed to disable the driver
outputs when a junction temperature of 150°C is reached. As
the device cools, the drivers reenable at a temperature of 140°C.
TRUTH TABLES
The truth tables in this section use the abbreviations listed
in Table 8.
Table 8. Truth Table Abbreviations
Letter Description
H High level
X Don’t care
Z High impedance (off)
NC Disconnected
Table 9. Transmitting
Supply Status Input Outputs
V
DD1
V
DD2
TxD State CANH CANL V
DD2SENSE
On On L Dominant H L L
On On H Recessive Z Z L
On On Floating Recessive Z Z L
On Off L I I I H
Table 10. Receiving
Supply Status Inputs Outputs
V
DD1
V
DD2
V
ID
= CANH − CANL Bus State RxD V
DD2SENSE
On On
≥0.9 V
Dominant L L
On On ≤0.5 V Recessive H L
On On 0.5 V < V
ID
< 0.9 V I I L
On On Inputs open Recessive H L
Off On X X I I
On Off X X H H
