DC2581A-B Datasheet DC2581A-A, DC2581A-B | P1-P3

dc2581af

DEMO MANUAL DC2581A

DESCRIPTION

LTC2341

16-/18-Bit, Dual 666ksps, SAR ADC

Demonstration circuit 2581A shows the proper way to drive

the LT C

2341 ADC. The LTC2341 is a low noise, high speed,

simultaneous sampling 16-/18-bit successive approximation

™

interface that allows conversion-by-conversion control of

the input voltage span on a per-channel basis. An internal

2.048V reference and 2× buffer simplify basic operation

while an external reference can be used to increase the input

range and the SNR of the ADC.

The DC2581A demonstrates the DC and AC performance of

the LTC2341 in conjunction with the DC590/DC2026 and

DC890 data collection boards. Use the DC590/DC2026 to

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and PScope,

QuikEval and SoftSpan are trademarks of Linear Technology Corporation. All other trademarks

are the property of their respective owners.

demonstrate DC performance such as peak-to-peak noise

and DC linearity. Use the DC890 if precise sampling rates

are required or to demonstrate AC performance such as

SNR, THD, SINAD and SFDR. The DC2581A is intended to

demonstrate recommended grounding, component place

ment and selection, routing and bypassing for this ADC. A

suggested driver circuit for the analog inputs is also presented.

Design files for this circuit board including the schematic,

layout and BOM are available at

http://www.linear.com/demo/DC2581A

Figure 1. DC2581A Connection Diagram

dc2581af

DEMO MANUAL DC2581A

DC890 QUICK START PROCEDURE

Check to make sure that all jumpers are set to their default

settings as described in the DC2581A Jumpers section of

this manual. The default connections configure the ADC to

use the onboard reference and regulators to generate all

the required bias voltages. The analog inputs by default are

DC coupled. Connect the DC2581A to a DC890 USB High

Speed Data Collection Board using connector P1. Then,

connect the DC890 to a host PC with a standard USB A/B

cable. Apply ±9V to the indicated terminals. Then apply

a low jitter signal source to J5 and J6. Use J7 to route

the signal sources of J5 and J6 to the desired AIN0-AIN1

inputs. Observe the recommended input voltage range

for each analog input. Connect a low jitter 2.5V

P-P

sine

wave or square wave to connector J1. See the Assembly

Options table for the appropriate clock frequency. Note

that J1 has a 50Ω termination resistor to ground.

Run the PScope

™

software (Pscope.exe version K91 or

later) which can be downloaded from www.linear.com/

designtools/software.

Complete software documentation is available from the

Help menu. Updates can be downloaded from the

Tools

menu. Check for updates periodically as new features

may be added.

The PScope software should recognize the DC2581A and

configure itself automatically.

Click the Collect button (See Figure 3) to begin acquiring

data. The Collect button then changes to Pause, which

can be clicked to stop data acquisition.

DC590/DC2026 QUICK START PROCEDURE

IMPORTANT! To avoid damage to the DC2581A, make

sure that VCCIO (JP6 of the DC590, JP3 of the DC2026)

of the DC590/DC2026 is set to 3.3V before connecting

the DC590/DC2026 to the DC2581A.

To use the DC590/DC2026 with the DC2581A, it is necessary

to apply ±9V and ground to the ±9V and GND terminals of

the DC2581A. Connect the DC590/DC2026 to a host PC

with a standard USB A/B cable. Connect the DC2581A to

a DC590/DC2026 USB serial controller using the supplied

14-conductor ribbon cable. Apply a signal source to J5

and J6. Use J7 to route the signal sources of J5 and J6

to the desired AIN0-AIN1 inputs. No Clock is required on

J1 when using the DC590/DC2026. The clock signal is

provided by the DC590/DC2026.

Run the QuikEval software (quikeval.exe version K110 or

later) which is available from www.linear.com/designtools/

software. The correct control panel will be loaded auto

matically. Click the COLLECT button (Figure 6) to begin

reading the ADC.

ASSEMBLY OPTIONS

Assembly

Version U1 Part Number

Max Conversion

Rate

Number of

Channels

Number of

Bits

Max CLK IN

Frequency

CLK IN/fs

Ratio

DC2581A-A LTC2341-18 666ksps 2 18 60MHz 90

DC2581A-B LTC2341-16 666ksps 2 16 60MHz 90

dc2581af

DEMO MANUAL DC2581A

DC2581A SETUP

–

AIN0

–

R107

49.9Ω

U25B

LT6237IDD

U25A

LT6237IDD

C96

0.1µF

C94

1000pF

C98

OPT

C116

OPT

R129

R108

24.9Ω

R123

24.9Ω

C104

0.1µF

R124

49.9Ω

C100

39pF

C112

39pF

C102

1000pF

DC2581a F02

R113

0Ω

R119

DC Power

The DC2581A requires ±9VDC and draws +132mA/–52mA.

Most of the supply current is consumed by the FPGA, op

amps, regulators and discrete logic on the board. The

±9VDC input voltage powers the ADC through LT1763

regulators which provide protection against accidental

reverse bias. Additional regulators provide power for the

FPGA and op amps.

Clock Source

You must provide a low jitter 2.5V

P-P

sine or square wave

to the clock input, J1. The clock input is AC coupled so the

DC level of the clock signal is not important. A generator

such as the Rohde & Schwarz SMB100A high speed clock

source is recommended to drive the clock input. Even a

good generator can start to produce noticeable jitter at

low frequencies. Therefore it is recommended for lower

sample rates to divide down a higher frequency clock to

the desired sample rate. The ratio of clock frequency to

conversion rate is shown in the Assembly Options table. If

the clock input is to be driven with logic, it is recommended

that the 49.9Ω termination resistor (R4) be removed.

Driving R4 with discrete logic may result in slow rising

edges. These slow rising edges may compromise the

SNR

of the converter in the presence of high-amplitude higher

frequency input signals.

Data Output

Parallel data output from this board (0V to 2.5V default),

if not connected to the DC890, can be acquired by a logic

analyzer, and subsequently imported into a spreadsheet, or

mathematical package depending on what form of digital

signal processing is desired. Alternatively, the data can

be fed directly into an application circuit. Use pin 50 of

P1 to latch the data. The data should be latched using the

negative edge of this signal. The data output signal levels

at P1 can also be increased to 0V-3.3V if the application

circuit requires a higher voltage. This is accomplished by

moving JP2 to the 3.3V position.

Figure 2. 0V–4.096V Single-Ended to Fully Differential DC Coupled Driver

P1-P3 P4-P6 P7-P9 P10-P10

DC2581A-B

Mfr. #:

Buy DC2581A-B

Manufacturer:

Analog Devices Inc.

Description:

Data Conversion IC Development Tools LTC2341-16 Demo Board - Dual, 16-Bit, 66

Lifecycle:

New from this manufacturer.

Delivery:

DHL FedEx Ups TNT EMS

Payment:

T/T Paypal Visa MoneyGram Western Union

DC2581A-B

DC2581A-B

Products related to this Datasheet