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dc2581af
DEMO MANUAL DC2581A
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
DC2581A CONNECTORS
DC2581A JUMPERS
Definitions
JP1: REF selects INT or EXT reference for the ADC. The
default setting is INT.
JP2: VCCIO sets the output levels at P1 to either 3.3V
or 2.5V. Use 2.5V to interface to the DC890 which is the
default setting. Use 3.3V to interface to the DC2026.
JP3: I/O selects LVDS or CMOS logic levels. The default
setting is CMOS. Only CMOS is currently supported.
Definitions
P1: DC890 interface is used to communicate with the
DC890 controller.
J1: CLK provides the master clock for the DC2581A when
interfaced to the DC890.
J2: FPGA PROGRAM is used to program the FPGA. This
is for factory use only.
JP4: EEPROM is for factory use only. The default posi
-
tion is WP.
JP5, JP8: AIN0-AIN1 can be used to short individual AIN
inputs to ground or can be used drive the individual AIN
inputs. The default is to leave these open.
JP13-JP14: Coupling selects AC or DC coupling for V
IN1
and V
IN2
. Default setting is DC.
JP15: Sets V
CM
for the single-end to differential drivers
of AIN0-AIN1
J3: JTAG is for factory
use only.
J4: DC590/DC2026 interface is used to communicate with
the DC2026 Linduino controller or DC590.
J5 and J6: Provide analog input voltages to AIN0-AIN1
of the ADC.
J7: Routes the signals of J5 and J6 to AIN0-AIN1.
