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L6562
Table 4. Pin Description
N° Pin Function
1 INV Inverting input of the error amplifier. The information on the output voltage of the PFC pre-
regulator is fed into the pin through a resistor divider.
2 COMP Output of the error amplifier. A compensation network is placed between this pin and INV (pin
#1) to achieve stability of the voltage control loop and ensure high power factor and low THD.
3 MULT Main input to the multiplier. This pin is connected to the rectified mains voltage via a resistor
divider and provides the sinusoidal reference to the current loop.
4 CS Input to the PWM comparator. The current flowing in the MOSFET is sensed through a resistor,
the resulting voltage is applied to this pin and compared with an internal sinusoidal-shaped
reference, generated by the multiplier, to determine MOSFET’s turn-off.
5 ZCD Boost inductor’s demagnetization sensing input for transition-mode operation. A negative-going
edge triggers MOSFET’s turn-on.
6 GND Ground. Current return for both the signal part of the IC and the gate driver.
7 GD Gate driver output. The totem pole output stage is able to drive power MOSFET’s and IGBT’s
with a peak current of 600 mA source and 800 mA sink. The high-level voltage of this pin is
clamped at about 12V to avoid excessive gate voltages in case the pin is supplied with a high
Vcc.
8 Vcc Supply Voltage of both the signal part of the IC and the gate driver. The supply voltage upper
limit is extended to 22V min. to provide more headroom for supply voltage changes.
Table 5. Electrical Characteristics
(T
j
= -25 to 125°C, V
CC
= 12, C
O
= 1 nF; unless otherwise specified)
Symbol Parameter Test Condition Min. Typ. Max. Unit
SUPPLY VOLTAGE
V
CC
Operating range After turn-on 10.3 22 V
V
CCon
Turn-on threshold
(1)
11 12 13 V
V
CCOff
Turn-off threshold
(1)
8.7 9.5 10.3 V
Hys Hysteresis 2.2 2.8 V
V
Z
Zener Voltage I
CC
= 20 mA 22 25 28 V
SUPPLY CURRENT
I
start-up
Start-up Current Before turn-on, V
CC
=11V 40 70 µA
I
q
Quiescent Current After turn-on 2.5 3.75 mA
I
CC
Operating Supply Current @ 70 kHz 3.5 5 mA
I
q
Quiescent Current During OVP (either static or
dynamic) or V
ZCD
=150 mV
2.2 mA
MULTIPLIER INPUT
I
MULT
Input Bias Current V
VFF
= 0 to 4 V -1 µA
V
MULT
Linear Operation Range 0 to 3 V
Output Max. Slope V
MULT
= 0 to 0.5V
V
COMP
= Upper clamp
1.65 1.9 V/V
K
Gain
(2)
V
MULT
= 1 V, V
COMP
= 4 V 0.5 0.6 0.7 1/V
ERROR AMPLIFIER
V
INV
Voltage Feedback Input
Threshold
T
j
= 25 °C 2.465 2.5 2.535 V
10.3 V < Vcc < 22 V
(1)
2.44 2.56
Line Regulation Vcc = 10.3 V to 22V 2 5 mV
I
INV
Input Bias Current V
INV
= 0 to 3 V -1 µA
V
CS
∆
V
MULT
∆
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