7/16
L6562
Figure 14. Vcs clamp vs. T
j
Figure 15. Start-up timer vs. T
j
Figure 16. ZCD clamp levels vs. T
j
Figure 17. ZCD source capability vs. T
j
Figure 18. Gate-drive output low saturation
Figure 19. Gate-drive output high saturation
Tj (°C)
V
CSx
(V)
-50 0 50 100 150
1
1.2
1.4
1.6
1.8
2
Vcc = 12 V
V
COMP
= Upper clamp
Tj (°C)
Tstart
(µs)
-50 0 50 100 150
100
110
120
130
140
150
Vcc = 12 V
Tj (°C)
V
ZCD
(V)
-50 0 50 100 150
0
1
2
3
4
5
6
7
Vcc = 12 V
I
ZCD
= ±2.5 mA
Upper clamp
Lower clamp
Tj (°C)
I
ZCDsrc
(mA)
-50 0 50 100 150
-8
-6
-4
-2
0
Vcc = 12 V
V
ZCD
= lower clamp
V
pin7
[V]
0 200 400 600 800 1,000
0
1
2
3
4
I
GD
[mA]
Tj = 25 °C
Vcc = 11 V
SINK
0 100 200 300 400 500 600 700
-4.5
-4
-3.5
-3
-2.5
-2
-1.5
V
pin7
[V]
I
GD
[mA]
Tj = 25 °C
Vcc = 11 V
SOURCE
Vcc - 2.0
Vcc - 2.5
Vcc - 3.0
Vcc - 3.5
Vcc - 4.0
L6562
8/16
Figure 20. Gate-drive clamp vs. T
j
Figure 21. UVLO saturation vs. T
j
Tj (°C)
Vpin7
clamp
(V)
-50 0 50 100 150
10
11
12
13
14
15
Vcc = 20 V
Tj (°C)
-50 0 50 100 150
0.5
0.6
0.7
0.8
0.9
1
1.1
Vcc = 0 V
Vpin7
(V)
4 Application Information
4.1 Overvoltage protection
Under steady-state conditions, the voltage control loop keeps the output voltage Vo of a PFC pre-regulator
close to its nominal value, set by the resistors R1 and R2 of the output divider. Neglecting ripple compo-
nents, the current through R1, I
R1
, equals that through R2, I
R2
. Considering that the non-inverting input of
the error amplifier is internally referenced at 2.5V, also the voltage at pin INV will be 2.5V, then:
.
If the output voltage experiences an abrupt change Vo > 0 due to a load drop, the voltage at pin INV will
be kept at 2.5V by the local feedback of the error amplifier, a network connected between pins INV and
COMP that introduces a long time constant to achieve high PF (this is why Vo can be large). As a result,
the current through R2 will remain equal to 2.5/R2 but that through R1 will become:
.
The difference current I
R1
=I'
R1
-I
R2
=I'
R1
-I
R1
=Vo/R1 will flow through the compensation network and en-
ter the error amplifier output (pin COMP). This current is monitored inside the L6562 and if it reaches about
37 µA the output voltage of the multiplier is forced to decrease, thus smoothly reducing the energy deliv-
ered to the output. As the current exceeds 40 µA, the OVP is triggered (Dynamic OVP): the gate-drive is
forced low to switch off the external power transistor and the IC put in an idle state. This condition is main-
tained until the current falls below approximately 10 µA, which re-enables the internal starter and allows
switching to restart. The output Vo that is able to trigger the Dynamic OVP function is then:
.
An important advantage of this technique is that the OV level can be set independently of the regulated
output voltage: the latter depends on the ratio of R1 to R2, the former on the individual value of R1. Another
advantage is the precision: the tolerance of the detection current is 12%, that is 12% tolerance on Vo.
Since Vo << Vo, the tolerance on the absolute value will be proportionally reduced.
Example: Vo = 400 V, Vo = 40 V. Then: R1=40V/40µA=1M; R2=1M·2.5/(400-2.5)=6.289k. The tol-
erance on the OVP level due to the L6562 will be 40·0.12=4.8V, that is 1.2% of the regulated value.
I
R2
2.5
R2
-------- I
R1
Vo 2.5
R1
----------------------===
I'
R1
Vo 2.5 Vo+
R1
----------------------------------------=
Vo R1 40 10
6
⋅⋅=
9/16
L6562
When the load of a PFC pre-regulator is very low, the output voltage tends to stay steadily above the nom-
inal value, which cannot be handled by the Dynamic OVP. If this occurs, however, the error amplifier out-
put will saturate low; hence, when this is detected, the external power transistor is switched off and the IC
put in an idle state (Static OVP). Normal operation is resumed as the error amplifier goes back into its lin-
ear region. As a result, the L6562 will work in burst-mode, with a repetition rate that can be very low.
When either OVP is activated the quiescent consumption of the IC is reduced to minimize the discharge
of the Vcc capacitor and increase the hold-up capability of the IC supply system.
4.2 THD optimizer circuit
The L6562 is equipped with a special circuit that reduces the conduction dead-angle occurring to the AC
input current near the zero-crossings of the line voltage (crossover distortion). In this way the THD (Total
Harmonic Distortion) of the current is considerably reduced.
A major cause of this distortion is the inability of the system to transfer energy effectively when the instan-
taneous line voltage is very low. This effect is magnified by the high-frequency filter capacitor placed after
the bridge rectifier, which retains some residual voltage that causes the diodes of the bridge rectifier to be
reverse-biased and the input current flow to temporarily stop.
Figure 22. THD optimization: standard TM PFC controller (left side) and L6562 (right side)
To overcome this issue the circuit embedded in the L6562 forces the PFC pre-regulator to process more
energy near the line voltage zero-crossings as compared to that commanded by the control loop. This will
result in both minimizing the time interval where energy transfer is lacking and fully discharging the high-
frequency filter capacitor after the bridge. The effect of the circuit is shown in figure 23, where the key
waveforms of a standard TM PFC controller are compared to those of the L6562.
Essentially, the circuit artificially increases the ON-time of the power switch with a positive offset added to
Imains
Vdrain
Imains
Vdrain
Input current Input current
MOSFET's drain voltage
MOSFET's drain voltage
Rectified mains voltage Rectified mains voltage
Input current
Input current

EVAL6562-375W

Mfr. #:
Manufacturer:
STMicroelectronics
Description:
Power Management IC Development Tools Eval for L6562D/N
Lifecycle:
New from this manufacturer.
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