LTC3831
10
3831fb
APPLICATIONS INFORMATION
and source pins. In addition, connect a 0.1µF decoupling
capacitor across R
IMAX
to fi lter switching noise. Other-
wise, noise spikes or ringing at Q1’s source can cause the
actual current limit to be greater than the desired current
limit set point. Due to switching noise and variation of
R
DS(ON)
, the actual current limit trip point is not highly
accurate. The current limiting circuitry is primarily meant
to prevent damage to the power supply circuitry during
fault conditions. The exact current level where the limit-
ing circuit begins to take effect will vary from unit to unit
as the R
DS(ON)
of Q1 varies. Typically, R
DS(ON)
varies as
much as ±40% and with ±25% variation on the LTC3831’s
I
MAX
current, this can give a ±65% variation on the current
limit threshold.
The R
DS(ON)
is high if the V
GS
applied to the MOSFET is
low. This occurs during power up, when PV
CC1
is ramping
up. To prevent the high R
DS(ON)
from activating the cur-
rent limit, the LTC3831 disables the current limit circuit
if PV
CC1
is less than 2.5V above V
CC
. To ensure proper
operation of the current limit circuit, PV
CC1
must be at
least 2.5V above V
CC
when TG is high. PV
CC1
can go low
when TG is low, allowing the use of an external charge
pump to power PV
CC1
.
Oscillator Frequency
The LTC3831 includes an onboard current controlled os-
cillator that typically free-runs at 200kHz. The oscillator
frequency can be adjusted by forcing current into or out of
the FREQSET pin. With the pin fl oating, the oscillator runs
at about 200kHz. Every additional 1µA of current into/out
of the FREQSET pin decreases/increases the frequency by
10kHz. The pin is internally servoed to 1.265V, connect-
ing a 50k resistor from FREQSET to ground forces 25µA
out of the pin, causing the internal oscillator to run at
approximately 450kHz. Forcing an external 10µA current
into FREQSET cuts the internal frequency to 100kHz. An
internal clamp prevents the oscillator from running slower
than about 50kHz. Tying FREQSET to V
CC
forces the chip
to run at this minimum speed.
Shutdown
The LTC3831 includes a low power shutdown mode,
controlled by the logic at the SHDN pin. A high at SHDN
allows the part to operate normally. A low level at SHDN
for more than 100µs forces the LTC3831 into shutdown
mode. In this mode, all internal switching stops, the COMP
and SS pins pull to ground and Q1 and Q2 turn off. The
LTC3831 supply current drops to <10µA, although off-
state leakage in the external MOSFETs may cause the total
V
IN
current to be somewhat higher, especially at elevated
temperatures. If SHDN returns high, the LTC3831 reruns
a soft-start cycle and resumes normal operation.
External Clock Synchronization
The LTC3831 SHDN pin doubles as an external clock input
for applications that require a synchronized clock. An
internal circuit forces the LTC3831 into external synchro-
nization mode if a negative transition at the SHDN pin is
detected. In this mode, every negative transition on the
SHDN pin resets the internal oscillator and pulls the ramp
signal low. This forces the LTC3831 internal oscillator to
lock to the external clock frequency.
The LTC3831 internal oscillator can be externally syn-
chronized from 100kHz to 500kHz. Frequencies above
300kHz can cause a decrease in the maximum obtainable
duty cycle as rise/fall time and propagation delay take up
a larger percentage of the switch cycle. The low period of
this clock signal must not be >100µs or else the LTC3831
enters into the shutdown mode.
Figure 4 describes the operation of the external synchroni-
zation function. A negative transition at the SHDN pin forces
the internal ramp signal low to restart a new PWM cycle.
Notice that the ramp amplitude is lowered as the external
clock frequency goes higher. The effect of this decrease
in ramp amplitude increases the open-loop gain of the
Figure 3. Current Limit Setting
+
+
12
13
LTC3831
CC
12
µA
0.1µF
Q2
C
OUT
3831 F03
C
IN
V
IN
V
OUT
BG
I
MAX
R
IMAX
I
FB
1k
+
–
Q1
L
O
TG
