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LTC2392CUK-16#TRPBF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P26
LTC2392-16
16
239216fa
applications inFormation
down. The data from that conversion can be read after PD
= low is applied. In this mode power consumption drops
to a typical value of 175µW from 110mW. This mode can
be used if the LTC2392-16 is inactive for a long period of
time and the user wants to minimize the power dissipation.
Recovery from Power Shutdown Mode
Once the PD pin is returned to a low level, ending the
power shutdown request, the internal circuitry will begin
to power up. If the internal reference is used, the 2.6kΩ
output impedance with the 1µF bypass capacitor on the
REFIN/REFOUT pins will be the main time constant for
the power-on recovery time. If an external reference is
used, typically allow 5ms for recovery before initiating a
new conversion.
Power Dissipation vs Sampling Frequency
The power dissipation of the LTC2392-16 will decrease
as the sampling frequency is reduced when nap mode is
activated. See Figure 7. In nap mode, a portion of the cir-
cuitry on the LTC2392-16 is turned off after a conversion
has been completed. Increasing the time allowed between
conversions lowers the average power.
TIMING AND CONTROL
The LTC2392-16 conversion is controlled by CNVST. A
falling edge on CNVST
will start a conversion. CS and RD
control the digital interface on the LTC2392-16. When
either CS or RD is high, the digital outputs are high
impedance.
CNVST Timing
The LTC2392-16 conversion is controlled by CNVST. A
falling edge on CNVST will start a conversion. Once a
conversion has been initiated, it cannot be restarted until
the conversion is complete. For optimum performance
CNVST should be a clean low jitter signal. Converter status
is indicated by the BUSY output which remains high while
the conversion is in progress. To ensure no errors occur
in the digitized results return the rising edge either within
40ns from the start of the conversion or wait until after
the conversion has been completed. The CNVST timing
needed to take advantage of the reduced power mode of
operation is described in the Nap Mode section.
Internal Conversion Clock
The LTC2392-16 has an internal clock that is trimmed
to achieve a maximum conversion time of 1300ns. No
external adjustments are required and with a maximum
acquisition time of 685ns, a throughput performance of
500ksps is guaranteed.
DIGITAL INTERFACE
The LTC2392-16 allows both parallel and serial digital
interfaces. The flexible OVP supply
allows the
LTC2392-16
to communicate with any digital logic operating between
1.8V and 5V, including 2.5V and 3.3V systems.
Figure 7. Power Dissipation of the LTC2392-16
Decreases with Decreasing Sampling Frequency
SAMPLING FREQUENCY (kHz)
10
POWER SUPPLY CURRENT (mA)
20
30
5
15
25
0.1 10 100 1000
239216 G15
0
1
LTC2392-16
17
239216fa
applications inFormation
Parallel Modes
The parallel output data interface is active when the
SER/PAR pin is tied low and when both CS and RD are low.
The output data can be read as a 16-bit word as shown
in Figures 8, 9 and 10 or it can be read as two 8-bit bytes
by using the BYTESWAP pin. As shown in Figure 11, with
the BYTESWAP pin low, the first eight MSBs are output
on the D15 to D8 pins and the eight LSBs are output on
the D7 to DO pins. When BYTESWAP is taken high, the
eight LSBs now are output on the D15 to D8 pins and the
eight MSBs are output on the D7 to D0 pins.
Serial Modes
The serial output data interface is active when the
SER/PAR pin is tied high and when both CS and RD are
low. The serial output data will be clocked out on the
SDOUT pin when an external clock is applied to the SCLK
pin. Clocking out the data after the conversion will yield
the best performance. With a shift clock frequency of at
least 25MHz, a 500ksps throughput is achieved. The serial
output data changes state on the rising
edge of SCLK and
can
be captured on the falling edge of SCLK. D15 remains
valid till the first rising edge of shift clock after the first
falling edge of shift clock. The non-active digital outputs
are high impedance when operating in the serial mode.
If CS and RD are used to gate the serial output data, the
full conversion result should be read before CS and RD
are returned to a high level.
The SDIN input pin is used to daisychain multiple con-
verters. This is useful for applications where hardware
constraints may limit the number of lines needed to
interface to a large number of converters. For example,
if two devices are cascaded, the MSB of the first device
will appear at the output after 17 SCLK cycles. The first
MSB is clocked in on the falling edge of the first SCLK.
See Figure 12.
Data Format
When OB/2C is high, the digital output is offset binary.
When low, the MSB is inverted resulting in two’s comple-
ment output. This pin is active in both the parallel and
serial modes of operation.
Reset
When the RESET pin is high, the LTC2392-16 is reset, and
if this occurs
during a conversion, the conversion is halted
and
the data bus is put into Hi-Z mode. In reset, requests
for new conversions are ignored. Once RESET returns low,
the LTC2392-16 is ready to start a new conversion after
the acquisition time plus 1µs has been met. See Figure 13.
Figure 8. Read the Parallel Data Continuously.
The Data Bus is Always Driven and Can’t Be Shared
CS = RD = 0
t
4
t
6
t
16
t
CONV
CNVST
BUSY
DATA BUS D[15:0]
PREVIOUS CONVERSION NEW
239216 F08
LTC2392-16
18
239216fa
applications inFormation
Figure 9. Read the Parallel Data After the Conversion
Figure 10. Read the Parallel Data During the Conversion
Figure 11. 8-Bit Parallel Interface Using the BYTESWAP Pin
RD
BUSY
DATA BUS D[15:0]
Hi-Z
CURRENT
CONVERSION
t
17
t
18
239216 F09
Hi-Z
CS
CS = 0
CNVST, RD
BUSY
DATA BUS D[15:0]
Hi-Z
t
6
t
17
t
18
t
4
t
CONV
PREVIOUS
CONVERSION
Hi-Z
239216 F09
CS, RD
BYTESWAP
D[15:8]
HIGH BYTE LOW BYTE
8-BIT INTERFACE
Hi-Z Hi-Z
239216 F11
t
17
t
17
t
18
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P26

LTC2392CUK-16#TRPBF

Mfr. #:
Buy LTC2392CUK-16#TRPBF
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 5V 16-bit 500Ksps Int Ref Parallel / Serial SAR ADC in QFN-48
Lifecycle:
New from this manufacturer.
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