LTC2392-16
5
239216fa
timing characteristics
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at T
A
= 25°C. (Note 4)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
f
SMPL
Sampling Frequency
l
500 ksps
t
CONV
Conversion Time
l
1300 ns
t
ACQ
Acquisition Time
l
685 ns
t
4
CNVST Low Time
l
20 ns
t
5
CNVST High Time
l
250 ns
t
6
CNVST↓ to BUSY Delay
C
L
= 15pF
l
15 ns
t
7
RESET Pulse Width
l
5 ns
t
8
SCLK Period (Note 9)
l
12.5 ns
t
9
SCLK High Time
l
4 ns
t
10
SCLK Low Time
l
4 ns
t
r
, t
f
SCLK Rise and Fall Times (Note 10) 1 µs
t
11
SDIN Setup Time
l
2 ns
t
12
SDIN Hold Time
l
1 ns
t
13
SDOUT Delay After SCLK↑
C
L
= 15pF
l
2 8 ns
t
14
SDOUT Delay After CS↓
l
8 ns
t
15
CS↓ to SCLK Setup Time
l
20 ns
t
16
Data Valid to BUSY↓
l
1 ns
t
17
Data Access Time after RD↓ or BYTESWAP↑
l
10 ns
t
18
Bus Relinquish Time
l
10 ns
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to ground.
Note 3: When these pin voltages are taken below ground or above
AVP, DVP or OVP, they will be clamped by internal diodes. This product
can handle input currents up to 100mA below ground or above AVP,
DVP
or OVP without latchup.
Note 4:
AVP = DVP = OVP = 5V, f
SMPL
= 500ksps, external reference equal
to 4.096V unless otherwise noted.
Note 5: Recommended operating conditions.
Note 6: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 7: Bipolar zero error is the offset voltage measured from –0.5LSB
when the output code flickers between 0000 0000 0000 0000 and 1111
1111 1111 1111. Bipolar full-scale error is the worst-case of –FS or +FS
untrimmed deviation from ideal first and last code transitions and includes
the effect of offset error.
Note 8: All specifications in dB are referred to a full-scale ±4.096V input
with a 4.096V reference voltage.
Note 9: t
13
of 8ns maximum allows a shift clock frequency up to
2 • (t
13
+ t
SETUP
) for falling edge capture with 50% duty cycle and up to
80MHz for rising capture. t
SETUP
is the set-up time of the receiving logic.
Note 10: Guaranteed by design.
Note 11: Temperature coefficient is calculated by dividing the maximum
change in output voltage by the specified temperature range.
4V
0.5V
50% 50%
239216 F01
0.5V
4V
0.5V
4V
t
DELAY
t
WIDTH
t
DELAY
Figure 1. Voltage Levels for Timing Specifications
