HEF4094B_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 3 — 4 July 2013 9 of 18
NXP Semiconductors HEF4094B-Q100
8-stage shift-and-store register
11. Waveforms
Measurement points are given in Table 9.
Logic levels: V
OL
and V
OH
are typical output voltage levels that occur with the output load.
Fig 7. Clock to outputs propagation delays, and clock pulse width and maximum frequency
1/f
max
t
W
t
PHL
t
PLH
V
I
GND
V
OH
V
OL
QPn, QS1 output
CP input
V
M
V
M
001aaf113
t
PHL
t
PLH
V
OH
V
OL
QS2 output
V
M
Table 9. Measurement points
Supply voltage Input Output
V
DD
V
M
V
M
V
X
V
Y
5 V to 15 V 0.5V
DD
0.5V
DD
0.1V
DD
0.9V
DD
Measurement points are given in Table 9.
Logic levels: V
OL
and V
OH
are typical output voltage levels that occur with the output load.
Fig 8. Strobe to output propagation delays, and strobe pulse width, set up and hold times
t
W
t
PHL
t
PLH
V
I
GND
V
OH
V
OL
QPn output
STR input
V
M
V
M
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