HEF4094B_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 3 — 4 July 2013 4 of 18
NXP Semiconductors HEF4094B-Q100
8-stage shift-and-store register
5.2 Pin description
6. Functional description
[1] At the positive clock edge, the information in the 7th register stage is transferred to the 8th register stage and the QSn outputs.
H = HIGH voltage level; L = LOW voltage level; X = don’t care;
= positive-going transition; = negative-going transition;
Z = HIGH-impedance OFF-state; NC = no change;
Q6S = the data in register stage 6 before the LOW to HIGH clock transition;
Q7S = the data in register stage 7 before the HIGH to LOW clock transition.
Table 2. Pin description
Symbol Pin Description
STR 1 strobe input
D 2 data input
CP 3 clock input
QP0 to QP7 4, 5, 6, 7, 14, 13, 12, 11 parallel output
V
SS
8 ground supply voltage
QS1 9 serial output
QS2 10 serial output
OE 15 output enable input
V
DD
16 supply voltage
Table 3. Function table
[1]
Inputs Parallel outputs Serial outputs
CP OE STR D QP0 QPn QS1 QS2
LXXZZQ6SNC
LXXZZNCQ7S
HLXNCNCQ6SNC
HHLLQPn 1Q6S NC
HHHHQPn 1Q6S NC
H H H NCNCNCQ7S
