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HEF4094BTT-Q100J

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19
HEF4094B_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 3 — 4 July 2013 6 of 18
NXP Semiconductors HEF4094B-Q100
8-stage shift-and-store register
9. Static characteristics
Table 6. Static characteristics
V
SS
= 0 V; V
I
=V
SS
or V
DD
; unless otherwise specified.
Symbol Parameter Conditions V
DD
T
amb
= 40 C T
amb
= +25 C T
amb
= +85 C T
amb
= +125 C Unit
Min Max Min Max Min Max Min Max
V
IH
HIGH-level
input voltage
I
O
< 1 A 5 V 3.5 - 3.5 - 3.5 - 3.5 - V
10 V7.0-7.0-7.0- 7.0 -V
15 V 11.0 - 11.0 - 11.0 - 11.0 - V
V
IL
LOW-level
input voltage
I
O
< 1 A 5 V - 1.5 - 1.5 - 1.5 - 1.5 V
10 V - 3.0 - 3.0 - 3.0 - 3.0 V
15 V - 4.0 - 4.0 - 4.0 - 4.0 V
V
OH
HIGH-level
output voltage
I
O
< 1 A 5 V 4.95 - 4.95 - 4.95 - 4.95 - V
10 V 9.95 - 9.95 - 9.95 - 9.95 - V
15 V 14.95 - 14.95 - 14.95 - 14.95 - V
V
OL
LOW-level
output voltage
I
O
< 1 A 5 V - 0.05 - 0.05 - 0.05 - 0.05 V
10 V - 0.05 - 0.05 - 0.05 - 0.05 V
15 V - 0.05 - 0.05 - 0.05 - 0.05 V
I
OH
HIGH-level
output current
V
O
= 2.5 V 5 V - 1.7 - 1.4 - 1.1 - 1.1 mA
V
O
= 4.6 V 5 V - 0.64 - 0.5 - 0.36 - 0.36 mA
V
O
= 9.5 V 10 V - 1.6 - 1.3 - 0.9 - 0.9 mA
V
O
= 13.5 V 15 V - 4.2 - 3.4 - 2.4 - 2.4 mA
I
OL
LOW-level
output current
V
O
= 0.4 V 5 V 0.64 - 0.5 - 0.36 - 0.36 - mA
V
O
= 0.5 V 10 V 1.6 - 1.3 - 0.9 - 0.9 - mA
V
O
= 1.5 V 15 V 4.2 - 3.4 - 2.4 - 2.4 - mA
I
OZ
OFF-state
output current
QPn output
is HIGH;
V
O
=15V
15 V - 0.4 - 0.4 - 12 - 12 A
I
I
input leakage
current
15 V - 0.1 - 0.1 - 1.0 - 1.0 A
I
DD
supply current all valid input
combinations;
I
O
=0A
5 V - 5 - 5 - 150 - 150 A
10 V - 10 - 10 - 300 - 300 A
15 V - 20 - 20 - 600 - 600 A
C
I
input
capacitance
---7.5-- - -pF
HEF4094B_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 3 — 4 July 2013 7 of 18
NXP Semiconductors HEF4094B-Q100
8-stage shift-and-store register
10. Dynamic characteristics
Table 7. Dynamic characteristics
V
SS
= 0 V; T
amb
= 25
C; for test circuit see Figure 11; unless otherwise specified.
Symbol Parameter Conditions V
DD
Extrapolation formula Min Typ Max Unit
t
PHL
HIGH to LOW
propagation delay
CP to QS1;
see Figure 7
5 V
[1]
108 ns + (0.55 ns/pF)C
L
- 135 270 ns
10 V 54 ns + (0.23 ns/pF)C
L
- 65 130 ns
15 V 42 ns + (0.16 ns/pF)C
L
- 50 100 ns
CP to QS2;
see Figure 7
5 V 78 ns + (0.55 ns/pF)C
L
- 105 210 ns
10 V 39 ns + (0.23 ns/pF)C
L
- 50 100 ns
15 V 32 ns + (0.16 ns/pF)C
L
-4080ns
CP to QPn;
see Figure 7
5 V 138 ns + (0.55 ns/pF)C
L
- 165 330 ns
10 V 64 ns + (0.23 ns/pF)C
L
- 75 150 ns
15 V 47 ns + (0.16 ns/pF)C
L
- 55 110 ns
STR to QPn;
see Figure 8
5 V 83 ns + (0.55 ns/pF)C
L
- 110 220 ns
10 V 39 ns + (0.23 ns/pF)C
L
- 50 100 ns
15 V 27 ns + (0.16 ns/pF)C
L
-3570ns
t
PLH
LOW to HIGH
propagation delay
CP to QS1;
see Figure 7
5 V
[1]
78 ns + (0.55 ns/pF)C
L
- 105 210 ns
10 V 39 ns + (0.23 ns/pF)C
L
- 50 100 ns
15 V 32 ns + (0.16 ns/pF)C
L
-4080ns
CP to QS2;
see Figure 7
5 V 78 ns + (0.55 ns/pF)C
L
- 105 210 ns
10 V 39 ns + (0.23 ns/pF)C
L
- 50 100 ns
15 V 32 ns + (0.16 ns/pF)C
L
-4080ns
CP to QPn;
see Figure 7
5 V 123 ns + (0.55 ns/pF)C
L
- 150 300 ns
10 V 59 ns + (0.23 ns/pF)C
L
- 70 140 ns
15 V 47 ns + (0.16 ns/pF)C
L
- 55 110 ns
STR to QPn;
see Figure 8
5 V 73 ns + (0.55 ns/pF)C
L
- 100 200 ns
10 V 34 ns + (0.23 ns/pF)C
L
-4590ns
15 V 27 ns + (0.16 ns/pF)C
L
-3570ns
t
t
transition time 5 V
[1]
10 ns + (1.00 ns/pF)C
L
- 60 120 ns
10 V 9 ns + (0.42 ns/pF)C
L
-3060ns
15 V 6 ns + (0.28 ns/pF)C
L
-2040ns
t
PZH
OFF-state to HIGH
propagation delay
OE to QPn;
see Figure 9
5 V - 40 80 ns
10 V - 25 50 ns
15 V - 20 40 ns
t
PZL
OFF-state to LOW
propagation delay
OE to QPn;
see Figure 9
5 V - 40 80 ns
10 V - 25 50 ns
15 V - 20 40 ns
t
PHZ
HIGH to OFF-state
propagation delay
OE to QPn;
see Figure 9
5 V - 75 150 ns
10 V - 40 80 ns
15 V - 30 60 ns
HEF4094B_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 3 — 4 July 2013 8 of 18
NXP Semiconductors HEF4094B-Q100
8-stage shift-and-store register
[1] The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (C
L
in pF).
t
PLZ
LOW to OFF-state
propagation delay
OE to QPn;
see Figure 9
5 V - 80 160 ns
10 V - 40 80 ns
15 V - 30 60 ns
t
su
set-up time D to CP;
see Figure 10
5 V 6030- ns
10 V 20 10 - ns
15 V 15 5 - ns
t
h
hold time D to CP;
see Figure 10
5 V +5 15 - ns
10 V 20 5 - ns
15 V 20 5 - ns
t
W
pulse width minimum LOW
clock pulse;
see Figure 7
5 V 6030- ns
10 V 30 15 - ns
15 V 24 12 - ns
minimum HIGH
strobe pulse;
see Figure 8
5 V 4020- ns
10 V 30 15 - ns
15 V 24 12 - ns
f
max
maximum frequency see Figure 7 5 V 5 10 - MHz
10 V 11 22 - MHz
15 V 1428- MHz
Table 7. Dynamic characteristics
…continued
V
SS
= 0 V; T
amb
= 25
C; for test circuit see Figure 11; unless otherwise specified.
Symbol Parameter Conditions V
DD
Extrapolation formula Min Typ Max Unit
Table 8. Dynamic power dissipation
V
SS
= 0 V; t
r
= t
f
20 ns; T
amb
= 25
C.
Symbol Parameter V
DD
Typical formula for P
D
(W) where:
P
D
dynamic power
dissipation
5 V P
D
= 2100 f
i
+ (f
o
C
L
) V
DD
2
f
i
= input frequency in MHz,
f
o
= output frequency in MHz,
C
L
= output load capacitance in pF,
V
DD
= supply voltage in V,
(f
o
C
L
) = sum of the outputs.
10 V P
D
= 9700 f
i
+ (f
o
C
L
) V
DD
2
15 V P
D
= 26000 f
i
+ (f
o
C
L
) V
DD
2
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19

HEF4094BTT-Q100J

Mfr. #:
Buy HEF4094BTT-Q100J
Manufacturer:
Nexperia
Description:
Counter Shift Registers HEF4094BTT-Q100/TSSOP16/REEL 1
Lifecycle:
New from this manufacturer.
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