AD9830
–11–
full-scale voltage developed across it does not exceed the voltage
compliance range. Since full-scale current is controlled by R
SET
,
adjustments to R
SET
can balance changes made to the load resistor.
However, if the DAC full-scale output current is significantly less
than 20 mA, the linearity of the DAC may degrade.
DSP and MPU Interfacing
The AD9830 has a parallel interface, with 16 bits of data being
loaded during each write cycle.
The frequency or phase registers are loaded by asserting the
WR
signal. The destination register for the 16-bit data is selected
using the address inputs A0, A1 and A2. The phase registers
are 12 bits wide so, only the 12 LSBs need to be valid—the
4 MSBs of the 16 bit word do not have to contain valid data.
Data is loaded into the AD9830 by pulsing
WR low, the data
being latched into the AD9830 on the rising edge of
WR. The
values of inputs A0, A1 and A2 are also latched into the
AD9830 on the
WR rising edge. The appropriate register is up-
dated on the next MCLK rising edge. To ensure that the
AD9830 contains valid data at the rising edge of MCLK, the
rising edge of the
WR pulse should not coincide with the rising
MCLK edge. The
WR pulse must occur several nanoseconds
before the MCLK rising edge. If the
WR rising edge occurs at
the MCLK rising edge, there is an uncertainty of one MCLK
cycle regarding the loading of the destination register—the desti-
nation register may be loaded with the new data immediately or
the destination register may be updated on the next MCLK ris-
ing edge. To avoid any uncertainty, the times listed in the speci-
fications should be complied with.
FSELECT, PSEL0 and PSEL1 are sampled on the MCLK
rising edge. Again, these inputs should be valid when an
MCLK rising edge occurs as there will be an uncertainty of one
MCLK cycle introduced otherwise. When these inputs change
value, there will be a pipeline delay before control is transferred
to the selected register—there will be a pipeline delay before the
analog output is controlled by the selected register. Similarly,
there is a delay when a new word is written to a register. PSEL0,
PSEL1, FSELECT and
WR have latencies of six MCLK cycles.
The flow chart in Figure 23 shows the operating routine for the
AD9830. When the AD9830 is powered up, the part should be
reset using
RESET. This will reset the phase accumulator to
zero so that the analog output is at midscale.
RESET does not
reset the phase and frequency registers. These registers will con-
tain invalid data and, therefore, should be set to zero by the user.
The registers to be used should be loaded, the analog output be-
ing f
MCLK
/2
32
× FREG where FREG is the value contained in
the selected frequency register. This signal will be phase shifted
by an amount 2π/4096 × PHASEREG where PHASEREG is the
value contained in the selected phase register. When FSELECT,
PSEL0 and PSEL1 are programmed, there will be a pipeline de-
lay of approximately 6 MCLK cycles before the analog output
reacts to the change on these inputs.
RESET
DATA WRITE
FREG<0, 1> = 0
PHASEREG<0, 1, 2, 3> = 0
DATA WRITE
FREG<0> = f
OUT
0/f
MCLK
*2
32
FREG<1> = f
OUT
1/f
MCLK
*2
32
PHASEREG<3:0> = DELTA PHASE<0, 1, 2, 3>
SELECT DATA SOURCES
SET FSELECT
SET PSEL0, PSEL1
DAC OUTPUT
V
OUT
= V
REFIN
*8*R
OUT
/R
SET*
(1 + SIN(2π(FREG*f
MCLK
*t/2
32
+ PHASEREG/2
12
)))
WAIT 6 MCLK CYCLES
CHANGE PHASE?
CHANGE FOUT?
CHANGE FREG?
YES
CHANGE PHASEREG? CHANGE PSEL0, PSEL1
YES
NO
NO
CHANGE FSELECT
YES
NO
YES
NO
Figure 23. Flow Chart for AD9830 Initialization and Operation
