AD9830
–5–
PIN DESCRIPTION
Mnemonic Function
POWER SUPPLY
AVDD Positive power supply for the analog section. A 0.1 µF capacitor should be connected between AVDD and
AGND. AVDD has a value of +5 V ± 5%.
AGND Analog Ground.
DVDD Positive power supply for the digital section. A 0.1 µF decoupling capacitor should be connected between DVDD
and DGND. DVDD has a value of +5 V ± 5%.
DGND Digital Ground.
ANALOG SIGNAL AND REFERENCE
IOUT,
IOUT Current Output. This is a high impedance current source. A load resistor should be connected between IOUT
and AGND.
IOUT should be either tied directly to AGND or through an external load resistor to AGND.
FS ADJUST Full-Scale Adjust Control. A resistor (R
SET
) is connected between this pin and AGND. This determines the mag-
nitude of the full-scale DAC current. The relationship between R
SET
and the full-scale current is as follows:
IOUT
FULL-SCALE
= 16 V
REFIN
/R
SET
V
REFIN
= 1.21 V nominal, R
SET
= 1 kΩ typical
REFIN Voltage Reference Input. The AD9830 can be used with either the on-board reference, which is available from pin
REFOUT, or an external reference. The reference to be used is connected to the REFIN pin. The AD9830 ac-
cepts a reference of 1.21 V nominal.
REFOUT Voltage Reference Output. The AD9830 has an on-board reference of value 1.21 V nominal. The reference is
made available on the REFOUT pin. This reference is used as the reference to the DAC by connecting REFOUT
to REFIN. REFOUT should be decoupled with a 10 nF capacitor to AGND.
COMP Compensation pin. This is a compensation pin for the internal reference amplifier. A 10 nF decoupling ceramic
capacitor should be connected between COMP and AVDD.
DIGITAL INTERFACE AND CONTROL
MCLK Digital Clock Input. DDS output frequencies are expressed as a binary fraction of the frequency of MCLK. The
output frequency accuracy and phase noise are determined by this clock.
FSELECT Frequency Select Input. FSELECT controls which frequency register, FREQ0 or FREQ1, is used in the phase ac-
cumulator. FSELECT is sampled on the rising MCLK edge. FSELECT needs to be in steady state when an
MCLK rising edge occurs. If FSELECT changes value when an MCLK rising edge occurs, there is an uncertainty
of one MCLK cycle as to when control is transferred to the other frequency register. To avoid any uncertainty, a
change on FSELECT should not coincide with an MCLK rising edge.
WR Write, Edge-Triggered Digital Input. The WR pin is used when writing data to the AD9830. The data is loaded
into the AD9830 on the rising edge of the
WR pulse. This data is then loaded into the destination register on the
MCLK rising edge. The
WR pulse rising edge should not coincide with the MCLK rising edge as there will be an
uncertainty of one MCLK cycle regarding the loading of the destination register with the new data. The
WR ris-
ing edge should occur before an MCLK rising edge. The data will then be transferred into the destination register
on the MCLK rising edge. Alternatively, the
WR rising edge can occur after the MCLK rising edge and the desti-
nation register will be loaded on the next MCLK rising edge.
D0–D15 Data Bus, Digital Inputs for destination registers.
A0–A2 Address Digital Inputs. These address bits are used to select the destination register to which the digital data is to
be written.
PSEL0, PSEL1 Phase Select Input. The AD9830 has four phase registers. These registers can be used to alter the value being in-
put to the SIN ROM. The contents of the phase register can be added to the phase accumulator output, the inputs
PSEL0 and PSEL1 selecting the phase register to be used. Like the FSELECT input, the AD9830 samples the
PSEL0 and PSEL1 inputs on the MCLK rising edge. Therefore, these inputs should be in steady state at the
MCLK rising edge or, there is an uncertainty of one MCLK cycle as to when control is transferred to the selected
phase register.
SLEEP Low Power Control, active low digital input. SLEEP puts the AD9830 into a low power mode. Internal clocks
are disabled and the DAC’s current sources and REFOUT are turned off. The AD9830 is re-enabled by taking
SLEEP high.
RESET Reset, active low digital input. RESET resets the phase accumulator to zero which corresponds to an analog
output of midscale.
