LOW SKEW, ÷1/÷2
DIFFERENTIAL-TO- 3.3V LVPECL CLOCK GENERATOR
8737-11 DATA SHEET
16 REVISION C 2/13/15
REVISION HISTORY SHEET
Rev Table Page Description of Change Date
A 3 Updated Figure 1, CLK_EN Timing Diagram. 10/17/01
A 3 Revised Figure 1, CLK_EN Timing Diagram. 10/31/01
A 8 Added Termination for LVPECL Outputs section. 6/3/02
A
12
6
7
Pin Description Table - revised MR description.
3.3V Output Load Test Circuit Diagram, revised VEE equation from
“-1.3V ± 0.135V” to “ -1.3V ± 0.165V”.
Revised Output Rise/Fall Time Diagram.
8/19/02
B
T1
T2
T5
2
2
4
5
6
8
9
10
Pin Description Table - revised MR description.
Pin Characteristics Table - changed C
IN
4pF max. to 4pF typical.
Absolute Maximum Ratings, updated Output rating.
AC Characteristics Table - added Additive Phase Jitter.
Added Additive Phase Jitter Section.
Updated LVPECL Output Termination drawings.
Added Differential Clock Input Interface section.
Added LVPECL Clock Input Interface section.
Updated format throughout the data sheet.
2/3/04
B
T9
1
15
Added Lead-Free bullet to Features section.
Added Lead-Free marking to Ordering Information table.
2/10/05
B
T9
1
15
Features Section - deleted bullet, “Industrial temperature information available
upon request.”
Ordering Information Table - added Lead-Free note.
3/18/05
C
T4D 5
11 - 12
LVPECL DC Characteristics Table -corrected V
OH
max. from V
CC
- 1.0V to
V
CC
- 0.9V; and V
SWING
max. from 0.9V to 1.0V.
Power Considerations - corrected power dissipation to refl ect V
OH
max in Table
4D.
4/13/07
C
T9 15
17
Updated datasheet’s header/footer with IDT from ICS.
Removed ICS prefi x from Part/Order Number column.
Added Contact Page.
8/9/10
C T9 15 Ordering Information - removed leaded devices - PDN CQ-13-02 2/13/15