GS9064-CKDE3

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GS9064
2.5 INPUT/OUTPUT CIRCUITS
All resistors in ohms, all capacitors in farads, unless otherwise shown.
Figure 3 Input Equivalent Circuit
Figure 4 MCLADJ Equivalent Circuit
Figure 5 CD
/MUTE Circuit
Figure 6 Output Circuit
Figure 7 CLI Output Circuit
Figure 8 Bypass Circuit
3k
3.6k
3k
3.6k
RC
SDI SDI
V
CC
MCLADJ
12k
150µ
+
-
7.5k
OUTPUT
STAGE
MUTE
CONTROL
V
CC
CD/MUTE
50
50
SDOSDO
10k
10k
V
CC
CLI
-
+
Bypass
Internal
Reference
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GS9064
2.6 TYPICAL PERFORMANCE CURVES
All resistors in ohms, all capacitors in farads, unless otherwise shown.
Figure 9 Power Consumption
Figure 10 CLI Voltage vs 8281 Cable Length, 270Mb/s
Figure 11 Input 8281, 280m, 270Mb/s
Figure 12 MCLADJ Input Voltage vs 1694A Cable Length,
270Mb/s
Figure 13 Typical Peak-to-Peak Jitter, PRN2
23
-1, 1694A, 270Mb/s
Figure 14 Output 8281, 280m, 270Mb/s
350
300
250
200
150
100
50
0
0 20 40 60 80
TEMPERATURE (˚C)
POWER CONSUMPTION (mW)
CABLE LENGTH (m)
CLI VOLTAGE (V)
3.5
3
2.5
2
1.5
0 50 100 150 200 250 300
CABLE LENGTH (m)
MCLADJ VOLTAGE (V)
2.0
0 50 100
150
200 250 300
2.5
3.0
3.5
1100
900
700
500
400
300
200
100
0
0 100 200 300 400
CABLE LENGTH (m)
JITTER (ps)
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GS9064
3. DETAILED DESCRIPTION
The GS9064 is a high speed bipolar IC designed to
equalize SD serial digital signals. The device can typically
equalize 350 meters of Belden
1694A cable
at 270Mb/s.
Powered from a single +3.3V or -3.3V power supply, the
device consumes approximately 240mW of power.
3.1 SERIAL DIGITAL INPUT
The SD serial digital input signal may be connected to the
input pins (SDI/SDI
) in either a differential or single ended
configuration. AC coupling of the inputs is recommended,
as the SDI and SDI
inputs are internally biased at
approximately +1.8 volts.
3.2 AUTOMATIC CABLE EQUALIZATION
The input signal passes through a variable gain equalizing
stage whose frequency response closely matches the
inverse of the cable loss characteristic. In addition, the vari-
ation of the frequency response with control voltage imitates
the variation of the inverse cable loss characteristic with
cable length.
The edge energy of the equalized signal is monitored by a
detector circuit which produces an error signal
corresponding to the difference between the desired edge
energy and the actual edge energy. This error signal is
integrated by both an internal and an external AGC filter
capacitor providing a steady control voltage for the gain
stage. As the frequency response of the gain stage is
automatically varied by the application of negative
feedback, the edge energy of the equalized signal is kept
at a constant level which is representative of the original
edge energy at the transmitter.
The equalized signal is also DC restored, effectively restor-
ing the logic threshold of the equalized signal to its correct
level independent of shifts due to AC coupling. The digital
output signals have a nominal voltage of 750mV
pp
differen-
tial, or 375mV
pp
single ended when terminated with 50Ω as
shown below in Figure 13.
Figure 15 Typical Output Voltage Levels
3.3 CABLE LENGTH INDICATION & CARRIER
DETECT/MUTE
The GS9064 incorporates an analog cable length indicator
(CLI) output and a programmable threshold output mute
(MCLADJ). In addition, a multi-function CD
/MUTE pin allows
control of the GS9064 MUTE functionality for SD inputs.
3.3.1 Cable Length Indicator
The voltage output of the CLI pin is a representation of the
amount of cable present at the inputs of the device. Figure
8 shows the CLI voltage versus cable length (signal
strength). At 270Mb/s with no cable length and 800mV input
signal levels, the CLI output voltage is approximately 2.5V.
As the cable length is increased, the CLI voltage
decreases, thereby providing an approximate correlation
between the CLI voltage and cable length
3.3.2 Programmable Mute Threshold
A voltage programmable mute threshold (MCLADJ) is
included to allow muting of the GS9064 output when a
selected cable length is reached. This feature allows the
device to distinguish between low amplitude SDI signals
and noise at its input.
Figure 10 shows the relationship between the voltage
applied to the MCLADJ pin and the input cable length
accepted by the GS9064. For consistent accurate results
this may need to be calibrated for each device. The
MCLADJ pin may be left unconnected for applications
where output muting is not required.
This feature has been designed for use in applications such
as routers where signal crosstalk and circuit noise cause
the equalizer to output erroneous data when no input signal
is actually present. The use of a Carrier Detect function with
a fixed internal reference does not solve this problem since
the signal to noise ratio on the circuit board could be
significantly less than the default signal detection level set
by the on-chip reference.
NOTE: MCLADJ and CLI are only recommended for data
rates up to 360 Mb/s.
3.3.3 Carrier Detect/Mute
Applying a HIGH INPUT to the CD/Mute pin forces the
GS9064 outputs to a muted condition. See the DC Electrical
Characteristics table for voltage levels. In this condition the
outputs are latched to the last logic level present at the
output to avoid signal crosstalk.
Applying a LOW INPUT to the CD
/Mute pin will force the
GS9064 outputs to remain active regardless of input cable
length or the voltage applied to the MCLADJ pin. See the DC
Electrical Characteristics table for voltage levels.
50 50
SDO
SDO
+187.5mV
-187.5mV
V
CM
= 2.925V
typical
+187.5mV
-187.5mV
V
CM
= 2.925V
typical

GS9064-CKDE3

Mfr. #:
Manufacturer:
Semtech
Description:
Equalizers SOIC-16N (50/tube)
Lifecycle:
New from this manufacturer.
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