CBTL02043A_CBTL02043B All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 4.1 — 30 March 2015 4 of 19
NXP Semiconductors
CBTL02043A; CBTL02043B
3.3 V, 2 differential channel, 2 : 1 MUX/deMUX switch
6.2 Pin description
[1] DHVQFN20 package die supply ground is connected to both GND pins and exposed center pad. GND pins
and the exposed center pad must be connected to supply ground for proper device operation. For
enhanced thermal, electrical, and board level performance, the exposed pad needs to be soldered to the
board using a corresponding thermal pad on the board and for proper heat conduction through the board,
thermal vias need to be incorporated in the printed-circuit board in the thermal pad region.
Table 3. Pin description
Symbol Pin Type Description
CBTL02043A CBTL02043B
A0_P 3 2 I/O channel 0, port A differential signal
input/output
A0_N 4 3 I/O
A1_P 7 6 I/O channel 1, port A differential signal
input/output
A1_N 8 7 I/O
B0_P 19 18 I/O channel 0, port B differential signal
input/output
B0_N 18 17 I/O
B1_P 17 14 I/O channel 1, port B differential signal
input/output
B1_N 16 13 I/O
C0_P 15 4 I/O channel 0, port C differential signal
input/output
C0_N 14 5 I/O
C1_P 13 8 I/O channel 1, port C differential signal
input/output
C1_N 12 9 I/O
SEL 9 12 CMOS
single-ended
input
operation mode select
SEL = LOW: A B
SEL = HIGH: A C
XSD 2 19 CMOS
single-ended
input
Shutdown pin; should be driven
LOW or connected to V
SS
for
normal operation. When HIGH, all
paths are switched off
(non-conducting high-impedance
state), and supply current
consumption is minimized.
V
DD
1, 6, 10 11, 16, 20 power positive supply voltage,
3.3 V ( 10 %)
GND
[1]
5, 11, 20,
center pad
1, 10, 15,
center pad
power supply ground
