CBTL02043A_CBTL02043B All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 4.1 — 30 March 2015 7 of 19
NXP Semiconductors
CBTL02043A; CBTL02043B
3.3 V, 2 differential channel, 2 : 1 MUX/deMUX switch
9. Limiting values
[1] Human Body Model: ANSI/EOS/ESD-S5.1-1994, standard for ESD sensitivity testing, Human Body Model -
Component level; Electrostatic Discharge Association, Rome, NY, USA.
[2] Charged Device Model: ANSI/EOS/ESD-S5.3-1-1999, standard for ESD sensitivity testing, Charged Device
Model - Component level; Electrostatic Discharge Association, Rome, NY, USA.
10. Recommended operating conditions
11. Static characteristics
[1] Typical values are at V
DD
= 3.3 V, T
amb
=25C, and maximum loading.
[2] Input leakage current is 50 A if differential pairs are pulled to HIGH and LOW.
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
V
DD
supply voltage 0.3 +4.6 V
T
case
case temperature 40 +85 C
T
stg
storage temperature 65 +150 C
V
ESD
electrostatic discharge voltage HBM
[1]
- 2000 V
CDM
[2]
- 1000 V
Table 6. Recommended operating conditions
Symbol Parameter Conditions Min Typ Max Unit
V
DD
supply voltage 3.0 3.3 3.6 V
V
I
input voltage - - V
DD
V
T
amb
ambient temperature operating in free air 40 - +85 C
Table 7. Static characteristics
V
DD
= 3.3 V
10 %; T
amb
=
40
C to +85
C; unless otherwise specified.
Symbol Parameter Conditions Min Typ
[1]
Max Unit
I
DD
supply current operating mode;
V
DD
= max.; XSD = LOW
-1.352.5mA
shutdown mode;
V
DD
= max.; XSD = HIGH
--1A
I
IH
HIGH-level input current V
DD
= max.; V
I
=V
DD
--5
[2]
A
I
IL
LOW-level input current V
DD
= max.; V
I
=GND - - 5
[2]
A
V
IH
HIGH-level input voltage SEL, XSD pins 0.65V
DD
-- V
V
IL
LOW-level input voltage SEL, XSD pins - - 0.35V
DD
V
V
I
input voltage differential pins - - 2.4 V
SEL, XSD pins - - V
DD
V
V
IC
common-mode input
voltage
0-2V
V
ID
differential input voltage peak-to-peak - - 1.6 V
CBTL02043A_CBTL02043B All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 4.1 — 30 March 2015 8 of 19
NXP Semiconductors
CBTL02043A; CBTL02043B
3.3 V, 2 differential channel, 2 : 1 MUX/deMUX switch
12. Dynamic characteristics
[1] Typical values are at V
DD
= 3.3 V; T
amb
=25C, and maximum loading.
Table 8. Dynamic characteristics
V
DD
=3.3V
10 %; T
amb
=
40
C to +85
C; unless otherwise specified.
Symbol Parameter Conditions Min Typ
[1]
Max Unit
DDIL differential insertion loss channel is OFF
f=4GHz - 20 - dB
f=100MHz - 50 - dB
channel is ON
f=4GHz - 1.3 - dB
f=100MHz - 0.5 - dB
DDNEXT differential near-end crosstalk adjacent channels are ON
f=4GHz - 35 - dB
f=100MHz - 65 - dB
B
3dB
3 dB bandwidth - 10 - GHz
DDRL differential return loss f = 4 GHz - 13.5 - dB
f=100MHz - 25 - dB
R
on
ON-state resistance V
DD
=3.3V; V
I
=2V;
I
I
=19mA
-6-
C
io(on)
on-state input/output capacitance - 1.5 - pF
t
PD
propagation delay from Port A to Port B, or
Port A to Port C, or vice versa
-60-ps
Switching characteristics
t
startup
start-up time supply voltage valid or
XSD going LOW to channel
specified operating conditions
--10ms
t
PZH
OFF-state to HIGH propagation delay - - 300 ns
t
PZL
OFF-state to LOW propagation delay - - 70 ns
t
PHZ
HIGH to OFF-state propagation delay - - 50 ns
t
PLZ
LOW to OFF-state propagation delay - - 50 ns
t
sk(dif)
differential skew time intra-pair - 5 - ps
t
sk
skew time inter-pair - - 35 ps
CBTL02043A_CBTL02043B All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 4.1 — 30 March 2015 9 of 19
NXP Semiconductors
CBTL02043A; CBTL02043B
3.3 V, 2 differential channel, 2 : 1 MUX/deMUX switch
Output 1 is for an output with internal conditions such that the output is LOW except when disabled
by the output control.
Output 2 is for an output with internal conditions such that the output is HIGH except when disabled
by the output control.
The outputs are measured one at a time with one transition per measurement.
Fig 5. Voltage waveforms for enable and disable times
002aag013
V
DD
t
PLZ
0.5V
DD
0.5V
DD
SEL
output 1
t
PZL
V
OL
0 V
0.85V
OH
V
OH
0.25V
OH
output 2
t
PZH
t
PHZ
V
OL
V
OH
0.85V
OH
0.25V
OH

CBTL02043BBQ,115

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
IC MUX/DEMUX 2:1 PCI 20DHVQFN
Lifecycle:
New from this manufacturer.
Delivery:
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