IS31IO7325
Integrated Silicon Solution, Inc. – www.issi.com 9
Rev. C, 01/03/2014
APPLICATION INFORMATION
FUNCTIONAL OVERVIEW
The IS31IO7325 is a Multi-function I/O driver operating
from a 2.4V to 5.5V supply with eight push-pull and
eight open-drain I/O ports. Each open-drain and
push-pull port is rated to sink 20mA at 0.22V
headroom, and the entire device is rated to sink
320mA at 0.22V headroom into all ports combined.
The outputs drive loads connected to supplies up to
+5.5V.
The IS31IO7325 is set to four I
2
C slave addresses
using the address select inputs AD0 and AD1, and is
accessed over an I
2
C serial interface up to 400kHz.
The RSTB input clears the serial interface in case of a
bus lockup, terminating any serial transaction to or
from the IS31IO7325.
The IS31IO7325 consists of input, output port registers,
configuration registers and interrupt control register. All
I/O ports offer latching transition detection when
configured as inputs. All input ports are continuously
monitored for changes.
A latching interrupt output, INTB, is programmed to
flag logic changes on ports used as inputs. Data
changes on any input port forces INTB to a logic-low.
Changing the I/O port level through the serial interface
does not cause an interrupt. The interrupt output INTB
is cleared successfully by reading the corresponding
input/output ports.
Ports default to logic-high or logic-low on power-up in
groups of four (see Table 1).
INITIAL POWER-UP
On power-up, the transition detection logic is reset,
and INTB is reset. The power-up default states of the
16 I/O ports are set according to the I2C slave address
selection inputs, AD0 and AD1 (see Table 1). For I/O
ports used as inputs, ensure that the default states are
logic-high so that the I/O ports power up in the high
impedance state.
POWER-ON RESET
The IS31IO7325 contains an integral power-on-reset
(POR) circuit that ensures all registers are reset to a
known state on power-up. When V
CC
rises above V
POR
(2.3V max), the POR circuit releases the registers and
2-wire interface for normal operation. When V
CC
drops
to less than V
POR
, the IS31IO7325 resets all register
contents to the POR defaults.
RSTB Input
The active-low RSTB input voids any I2C transaction
involving the IS31IO7325, forcing the IS31IO7325 into
the I2C STOP condition. A reset does not affect the
interrupt output.
STANDBY MODE
When the serial interface is idle, the IS31IO7325
automatically enters standby mode, drawing minimal
supply current.
I/O PORT INPUT TRANSITION DETECTION
All I/O ports configured as inputs are monitored for
changes since the expander was last accessed
through the serial interface. The open-drain interrupt
output, INTB, activates when one of the port pins
changes states and only when the pin is configured as
an input. The interrupt deactivates when the
input/output register is read. A pin configured as an
output does not cause an interrupt. Each 8-bit port
register is read independently; therefore, an interrupt
caused by port A (OD0~OD7) is not cleared by a read
of port B (PP0~PP7)’s register.
Changing an I/O from an output to an input may cause
a false interrupt to occur if the state of that I/O does not
match the content of output port register. The
IS31IO7325 has interrupt control register to avoid false
interrupt by setting the interrupt control register bit high
firstly, when the I/O state is stable, clear the interrupt
control register to enable the input transition detection
function.
ACCESSING THE IS31IO7325
Serial Addressing
The IS31IO7325 operates as a slave that sends and
receives data through a 2-wire interface. The interface
uses a serial data line (SDA) and a serial clock line
(SCL) to achieve bidirectional communication between
master(s) and slave(s). A master, typically a
microcontroller, initiates all data transfers to and from
the IS31IO7325, and generates the SCL clock that
synchronizes the data transfer (see Figure 2).
SDA operates as both an input and an open-drain
output. A pull up resistor, typically 4.7kΩ, is required on
SDA. SCL operates only as an input. A pull up resistor,
typically 4.7kΩ, is required on SCL if there are multiple
masters on the 2-wire interface, or if the master in a
single-master system has an open-drain SCL output.
Each transmission consists of a START condition sent
by a master, followed by the IS31IO7325’s 7-bit slave
addresses plus R/W bits, 1 or more data bytes, and
finally a STOP condition (see Figure 3).
START and STOP Conditions
Both SCL and SDA remain high when the interface is
not busy. A master signals the beginning of a
transmission with a START (S) condition by
transitioning SDA from high to low while SCL is high.
When the master has finished communicating with the
slave, the master issues a STOP (P) condition by
transitioning SDA from low to high while SCL is high.
The bus is then free for another transmission (see
Figure 3)
