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KAF-0402-AAA-CP-B2

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16
KAF−0402
www.onsemi.com
10
AC Operating Conditions
Table 9. CLOCK LEVELS
Description Symbol Level Minimum Nominal Maximum Units
Effective
Capacitance
Vertical CCD Clock − Phase 1
fV1
Low −10.5 −10 −9.5 V
6 nF (All fV1 Pins)
Vertical CCD Clock − Phase 1
fV1
High −0.5 0 1.0 V
6 nF (All fV1 Pins)
Vertical CCD Clock − Phase 2
fV2
Low −10.5 −10.0 −9.5 V
6 nF (All fV2 Pins)
Vertical CCD Clock − Phase 2
fV2
High −0.5 0 1.0 V
6 nF (All fV2 Pins)
Horizontal CCD Clock − Phase 1
fH1
Low −4.5 −4.0 −3.5 V 50 pF
Horizontal CCD Clock − Phase 1
fH1
Amplitude 9.5 10.0 10.5 V 50 pF
Horizontal CCD Clock − Phase 2
fH2
Low −4.5 −4.0 −3.5 V 50 pF
Horizontal CCD Clock − Phase 2
fH2
Amplitude 9.5 10.0 10.5 V 50 pF
Reset Clock
fR
Low −3.0 −2.0 −1.75 V 5 pF
Reset Clock
fR
Amplitude 5.0 6.0 7.0 V 5 pF
1. All pins draw less than 10 mA DC current.
2. Capacitance values relative to V
SUB
.
KAF−0402
www.onsemi.com
11
TIMING
Table 10. REQUIREMENTS AND CHARACTERISTICS
Description Symbol Minimum Nominal Maximum Units Notes
fH1, fH2 Clock Frequency
f
H
− 4 10 MHz 1, 2, 3
Pixel Period (1 Count) t
PIX
100 250 − ns
fH1, fH2 Set-up Time t
f
HS
0.5 1 −
ms
fV1, fV2 Clock Pulse Width t
f
V
1.5 2 −
ms
2
Reset Clock Pulse Width
t
f
R
10 20 − ns 4
Readout Time t
READOUT
43.7 107 − ms 5
Integration Time t
INT
− − − 6
Line Time t
LINE
84.1 206 −
ms
7
1. 50% duty cycle values.
2. CTE may degrade above the nominal frequency.
3. Rise and fall times (10/90% levels) should be limited to 5−10% of clock period. Crossover of register clocks should be between 40−60% of
amplitude.
4. fR should be clocked continuously.
5. t
READOUT
= (520 ⋅ t
LINE
)
6. Integration time (t
INT
) is user specified. Longer integration times will degrade noise performance due to dark signal fixed pattern and shot
noise.
7. t
LINE
= (3 ⋅ t
f
V
) + t
f
HS
+ (796 ⋅ t
PIX
) + t
PIX
Frame Timing
Figure 9. Frame Timing Diagram
Frame Timing
t
READOUT
t
INT
1 Frame = 520 Lines
52051921Line
fV1
fV2
fH1
fH2
KAF−0402
www.onsemi.com
12
Line Timing and Pixel Timing
Figure 10. Line and Pixel Timing Diagrams
Photoactive
Line Timing Detail Pixel Timing Detail
Line Content
Dark Reference
Dummy Pixels
1−10 11−14 15−782 783−794 795−796
V
SAT
Saturated pixel video output signal
V
DARK
Video output signal in no-light situation,
not zero due to J
DARK
V
PIX
Pixel video output signal level,
more electrons = more negative
V
ODC
Video level offset with respect to V
SUB
*
V
SUB
Analog ground
* See Image Acquisition section.
fV1
fV2
fH1
fH2
fR
1 Line = 796 Pixels
t
f
V
t
f
HS
t
PIX
796 Counts
t
f
V
fH1
fH2
fR
V
OUT
t
f
R
t
PIX
V
SAT
V
DARK
V
ODC
V
SUB
V
PIX
1 Count
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16

KAF-0402-AAA-CP-B2

Mfr. #:
Buy KAF-0402-AAA-CP-B2
Manufacturer:
ON Semiconductor
Description:
Image Sensors FULL FRAME CCD IMAGE SENSOR
Lifecycle:
New from this manufacturer.
Delivery:
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