NJM2594
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!
HOW TO DECREASE LEAKAGE LEVEL
By adjusting DC bias of SIGNAL INPUT terminal, carrier leakage level may be decreased. By adjusting DC bias of
CARRIER INPUT terminal, signal leakage level may be decreased. In actual circuit, it can be seen the case that
either of these adjustment is provided, not both.
LEAKAGE ADJUSTMENT CIRCUIT
!
EVALUATION PC BOARD
The evaluation PC board shown in next page is useful for your design and is intended to have more understanding
of the usage and performance of this device. Two kinds of board are prepared for two packages, SSOP and DMP,
respectively. Each board can be applied to two kinds of circuit, emitter-follower output type and collector output type,
as shown below. This circuit is the same as MEASUREMENT CIRCUIT. For other electrical conditions, it should be
necessary to reconsider each value of components, especially of capacitance.
Note that this board is not prepared to show the recommendation of pattern and parts layout.
● Emitter - follower output
● Collector output
Singal Input
Fs
Carrier Input
Fc
V+
4
3
2
1
5
6
7
8
10kΩ
220kΩ 220kΩ
Variable Resistor for
Signal Leakage Level
Adjustment
10kΩ
Variable Resistor for
Carrier Leakage Level
Adjustment
(1)
(2)
(3)
(5)
(4)
(6)
(7)
(8)
Signal Input
Fs
V+
Carrier Input
Fc
0.01uF
50Ω
50Ω
0.022uF
RL
0.01uF
4
3
2
1
5
6
7
8
Open
0.01uF
0.01uF
Output
(1)
(2)
(3)
(5)
(4)
(6)
(9)
(11)
(10)
(12)
0.022uF
Signal Input
Fs
Carrier Input
Fc
0.01uF
50Ω
50Ω
V+
0.01uF
4
3
2
1
5
6
7
8
Open
0.01uF
0.01uF
330Ω
4.3kΩ
47Ω
A
Output
(50Ω)