DS1672
5 of 15
AC ELECTRICAL CHARACTERISTICS
(V
CC
= 0V, T
A
= -40°C to +85°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
SCL Clock
Frequency
f
SCL
Fast mode 100 400
kHz
Standard mode 100
Between a STOP and
t
BUF
Fast mode 1.3
µs
Standard mode 4.7
(Repeated) START
t
HD:STA
Fast mode 0.6
µs
Standard mode 4.0
LOW Period of SCL
Clock
t
LOW
µs
Standard mode 4.7
HIGH Period of SCL
Clock
t
HIGH
Fast mode 0.6
µs
Standard mode 4.0
Repeated START
t
SU:STA
Fast mode 0.6
µs
Standard mode 4.7
Data Hold Time
(Notes 7, 8)
t
HD:DAT
Fast mode 0 0.9
µs
Standard mode 0
Data Setup Time
(Note 9)
t
SU:DAT
Fast mode 100
ns
Standard mode 250
SDA and SCL
t
R
Fast mode 20 + 0.1C
B
300
ns
Standard mode 1000
SDA and SCL
t
F
Fast mode 20 + 0.1C
B
300
ns
Standard mode 300
Setup Time for STOP
Condition
t
SU:STO
Fast mode 0.6
µs
Standard mode 4.0
Each Bus Line
C
B
400 pF
I/O Capacitance C
I/O
10 pF
Note 6: After this period, the first clock pulse is generated.
Note 7: A device must internally provide a hold time of at least 300ns for the SDA signal (referenced to the V
IHMIN
of the SCL signal) in
order to bridge the undefined region of the falling edge of SCL.
Note 8:The maximum t
HD:DAT
has only to be met if the device does not stretch the LOW period (t
LOW
) of the SCL signal.
Note 9: A fast-mode device can be used in a standard-mode system, but the requirement t
SU:DAT
≥ to 250ns must then be met. This will
automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW
period of the SCL signal, it must output the next data bit to the SDA line t
R
max + t
SU:DAT
= 1000 + 250 = 1250ns before the SCL
line is released.
Note 10: C
B
–Total capacitance of one bus line in pF.
