DS1672
9 of 15
trimmed. Additional error will be added by crystal frequency drift caused by temperature shifts. External
circuit noise coupled into the oscillator circuit may result in the clock running fast. Refer to Application
Note 5: “Crystal Considerations with Dallas Real-Time Clocks” for detailed information.
Address Map
The counter is accessed by reading or writing the first 4 bytes of the DS1672 (00h–03h). The control
register and trickle charger are accessed by reading or writing the appropriate register bytes as illustrated
in Table 2. If the master continues to send or request more data after the address pointer has reached 05h,
the address pointer will wrap around to location 00h.
Table 2. Registers
Power Control
The device is fully accessible and data can be written and ready only when V
CC
is greater than V
PF
.
However, when V
CC
falls below V
PF
, (point at which write protection occurs) the internal clock registers
are blocked from any access. If V
PF
is less than V
BACKUP
, the device power is switched from V
CC
to
V
BACKUP
when V
CC
drops below V
PF
. If V
PF
is greater than V
BACKUP
, the device power is switched from
V
CC
to V
BACKUP
when V
CC
drops below V
BACKUP
. Oscillator and counter operation are maintained from
the V
BACKUP
source until V
CC
is returned to nominal levels (see Table 3).
Table 3. Power Control
SUPPLY CONDITION
POWERED BY
V
CC
< V
PF
, V
CC
< V
BACKUP
V
CC
< V
PF
, V
CC
> V
BACKUP
V
CC
> V
PF
, V
CC
< V
BACKUP
V
CC
> V
PF
, V
CC
> V
BACKUP
Oscillator Control
The EOSC bit (bit 7 of the control register) controls the oscillator when in back-up mode. This bit when
set to logic 0 will start the oscillator. When this bit is set to a logic 1, the oscillator is stopped and the
DS1672 is placed into a low-power standby mode (I
BACKUP
) when in back-up mode. When the DS1672 is
powered by V
CC,
the oscillator is always on regardless of the status of the EOSC bit; however, the counter
is incremented only when EOSC is a logic 0.
Microprocessor Monitor
A temperature-compensated comparator circuit monitors the level of V
CC
. When V
CC
falls to the power-
fail trip point, the RST signal (open drain) is pulled active, and read/write access is inhibited. When V
CC
returns to nominal levels, the RST signal is kept in the active state for t
RPU
(typically) to allow the power
supply and microprocessor to stabilize. Note, however, that if the EOSC bit is set to a logic 1 (to disable
the oscillator during write protection), the reset signal will be kept in an active state for t
RPU
plus the
startup time of the oscillator.
