Si5018
10 Rev. 1.2
Functional Description
The Si5018 utilizes a phase-locked loop (PLL) to
recover a clock synchronous to the input data stream.
This clock is used to retime the data, and both the
recovered clock and data are output synchronously via
current mode logic (CML) drivers. Optimal jitter
performance is obtained by using Silicon Laboratories'
DSPLL™ technology to eliminate the noise entry points
caused by external PLL loop filter components.
DSPLL
™
The phase-locked loop structure (shown in "Typical
Application Schematic‚" on page 9) utilizes Silicon
Laboratories' DSPLL™ technology to eliminate the
need for external loop filter components found in
traditional PLL implementations. This is achieved by
using a digital signal processing (DSP) algorithm to
replace the loop filter commonly found in analog PLL
designs. This algorithm processes the phase detector
error term and generates a digital control value to adjust
the frequency of the voltage-controlled oscillator (VCO).
Because external loop filter components are not
required, sensitive noise entry points are eliminated
thus making the DSPLL less susceptible to board-level
noise sources that make SONET/SDH jitter compliance
difficult to attain.
PLL Self-Calibration
The Si5018 achieves optimal jitter performance by
using self-calibration circuitry to set the loop gain
parameters within the DSPLL. For the self-calibration
circuitry to operate correctly, the power supply voltage
must exceed 2.25 V when calibration occurs. For best
performance, the user should force a self-calibration
once the supply has stabilized on powerup.
A self-calibration can be initiated by forcing a high-to-
low transition on the power-down control input,
PWRDN/CAL, while a valid reference clock is supplied
to the REFCLK input. The PWRDN/CAL input should be
held high at least 1 µs before transitioning low to
guarantee a self-calibration. Several application circuits
that could be used to initiate a power-on self-calibration
are provided in Silicon Laboratories’ “AN42: Controlling
DSPLL™ Self-Calibration for the Si5020/5018/5010
CDR Devices and Si531x Clock Multiplier/Regenerator
Devices.”
Reference Clock Detect
The Si5018 CDR requires an external reference clock
applied to the REFCLK input for normal device
operation. When REFCLK is absent, the LOL alarm will
always be asserted when it has been determined that
no activity exists on REFCLK, indicating the lock status
of the PLL is unknown. Additionally, the Si5018 uses the
reference clock to center the VCO output frequency at
the OC-48/STM-16 data rate. The device will self-
configure for operation with one of three reference clock
frequencies. This eliminates the need to externally
configure the device to operate with a particular
reference clock.
The reference clock centers the VCO for a nominal
output between 2.488 GHz and 2.7 GHz. The VCO
frequency is centered at 16, 32, or 128 times the
reference clock frequency. Detection circuitry
continuously monitors the reference clock input to
determine whether the device should be configured for
a reference clock that is 1/16, 1/32, or 1/128 the
nominal VCO output. Approximate reference clock
frequencies are given in Table 7.
Forward Error Correction (FEC)
The Si5018 supports FEC in SONET OC-48 (SDH
STM-16) applications for data rates up to 2.7 Gbps. In
FEC applications, the appropriate reference clock
frequency is determined by dividing the input data rate
by 16, 32, or 128. For example, if an FEC code is used
that produces a 2.7 Gbps data rate, the required
reference clock would be 168.75 MHz, 84.375 MHz, or
21.09 MHz.
Lock Detect
The Si5018 provides lock-detect circuitry that indicates
whether the PLL has achieved frequency lock with the
incoming data. The circuit compares the frequency of a
divided-down version of the recovered clock with the
frequency of the applied reference clock (REFCLK). If
the recovered clock frequency deviates from that of the
reference clock by the amount specified in Table 4 on
page 7
, the PLL is declared out of lock, and the loss-of-
lock (LOL) pin is asserted high. In this state, the PLL will
periodically try to reacquire lock with the incoming data
stream. During reacquisition, the recovered clock may
drift over a ±600 ppm range relative to the applied
reference clock, and the LOL output alarm may toggle
until the PLL has reacquired frequency lock. Due to the
Table 7. Typical REFCLK Frequencies
OC-48/
STM-16
(2.488 GHz)
OC-48/STM-16 w/
15/14 FEC
(2.666 GHz)
Ratio of
VCO to
REFCLK
19.44 MHz 20.83 MHz 128
77.76 MHz 83.31 MHz 32
155.52 MHz 166.63 MHz 16
