Si5018
4 Rev. 1.2
Detailed Block Diagram
PWRDN/CAL
Calibration
DIN+
DIN–
CLKOUT+
CLKOUT–
DOUT+
DOUT–
LOL
REFCLK+
REFCLK–
Retime
Bias
Generation
REXT
DIN+
REFCLK+
RetimeRetime
Bias
Generation
Bias
Generation
Phase
Detector
Phase
Detector
Phase
Detector
A/D
DSP
VCO
CLK
Divider
n
Lock
Detector
c
c
Si5018
Rev. 1.2 5
Electrical Specifications
Figure 1. Differential Voltage Measurement (DIN, REFCLK, DOUT, CLKOUT)
Figure 2. Differential Clock to Data Timing
Figure 3. Differential DOUT and CLKOUT Rise/Fall Times
Table 1. Recommended Operating Conditions
Parameter Symbol Test Condition
Min
1
Typ
Max
1
Unit
Ambient Temperature T
A
–40 25 85 °C
Si5018 Supply Voltage
2
V
DD
2.375 2.5 2.625 V
Notes:
1. All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise stated.
2. The Si5018 specifications are guaranteed when using the recommended application circuit (including component
tolerance) shown in "Typical Application Schematic‚" on page 9.
Differential
Single-Ended Voltage
SIGNAL+
SIGNAL–
Differential Peak-to-Peak Voltage
Differential
Voltage Swing
(SIGNAL+) – (SIGNAL–)
V
IS
V
ID
,V
OD
(V
ID
= 2V
IS
)
V
t
V
ICM
,V
OCM
I/Os
DOUT
t
C-D
CLKOUT
DOUT,
CLKOUT
t
F
t
R
80%
20%
Si5018
6 Rev. 1.2
Table 2. DC Characteristics
(V
DD
=2.5V ±5%, T
A
= –40 to 85 °C)
Parameter Symbol Test Condition Min Typ Max Unit
Supply Current I
DD
108 122 mA
Power Dissipation P
D
270 320 mW
Common Mode Input Voltage (DIN, REFCLK)* V
ICM
varies with V
DD
—.80xV
DD
—V
Single Ended Input Voltage (DIN, REFCLK)* V
IS
See Figure 1 200 750 mV
PP
Differential Input Voltage Swing (DIN, REFCLK)* V
ID
See Figure 1 200 1500 mV
PP
Input Impedance (DIN, REFCLK) R
IN
Line-to-Line 84 100 116
Differential Output Voltage Swing (DOUT)
OC48
V
OD
100 Load
Line-to-Line
780 990 1260 mV
PP
Differential Output Voltage Swing (CLKOUT)
OC48
V
OD
100 Load
Line-to-Line
550 900 1260 mV
PP
Output Common Mode Voltage
(DOUT,CLKOUT)
V
OCM
100 Load
Line-to-Line
—V
DD
0.23
—V
Output Impedance (DOUT,CLKOUT) R
OUT
Single-ended 84 100 116
Output Short to GND (DOUT,CLKOUT) I
SC(–)
—2531mA
Output Short to V
DD
(DOUT,CLKOUT) I
SC(+)
–17.5 –14.5 mA
Input Voltage Low (LVTTL Inputs) V
IL
——.8V
Input Voltage High (LVTTL Inputs) V
IH
2.0 — V
Input Low Current (LVTTL Inputs) I
IL
——10µA
Input High Current (LVTTL Inputs) I
IH
——10µA
Output Voltage Low (LVTTL Outputs) V
OL
I
O
=2mA 0.4 V
Output Voltage High (LVTTL Outputs) V
OH
I
O
=2mA 2.4 V
Input Impedance (LVTTL Inputs) R
IN
10 k
PWRDN/CAL Leakage Current I
PWRDN
V
PWRDN
0.8 V 15 25 35 µA
*Note: The DIN and REFCLK inputs may be driven differentially or single-endedly. When driving single-endedly, the voltage swing
of the signal applied to the active input must exceed the specified minimum Differential Input Voltage Swing (V
ID
min), and
the unused input must be ac coupled to ground. When driving differentially, the difference between the positive and
negative input signals must exceed V
ID
min. (Each individual input signal needs to swing only half of this range.) In either
case, the voltage applied to any individual pin (DIN+, DIN–, REFCLK+, or REFCLK–) must not exceed the specified
maximum Input Voltage Range (V
IS
max).

SI5018-BM

Mfr. #:
Manufacturer:
Silicon Labs
Description:
IC CLOCK/DATA RECOVERY LP 20QFN
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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