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6
M-8888
Rev. 1
Distortion Calculations:
The M-8888 is capable of producing precise tone
bursts with minimal error in frequency (see the Actual
Frequecies vs Standard Requirements on page 5).
The internal summing amplifier is followed by a first-
order low-pass switched capacitor filter to minimize
harmonic components and intermodulation products.
The total harmonic distortion for a single tone can be
calculated using Equation 1, (see Equations on page
7), which is the ratio of the total power of all the extra-
neous frequencies to the power of the fundamental fre-
quency expressed as a percentage. The Fourier
components of the tone output correspond to V2f... Vnf
as measured on the output waveform. The total har-
monic distortion for a dual tone can be calculated
using Equation 2, (see Equations on page 7).
V
L
and V
H
correspond to the low-group and high-group
amplitude, respectively, and V
2
IMD
is the sum of all the
intermodulation components. The internal switched
capacitor filter following the D/A converter keeps dis-
tortion products down to a very low level.
DTMF Clock Circuit
The internal clock circuit is completed with the addition
of a standard 3.579545 MHz television color burst
crystal. A number of M-8888 devices can be connect-
ed as shown in the Common Crystal Connection on
page 7 using only one crystal.
Microprocessor Interface
The M-8888 uses a microprocessor interface that
allows precise control of transmitter and receiver func-
tions. Five internal registers are associated with the
microprocessor interface, which can be subdivided
into three categories: data transfer, transceiver control,
and transceiver status. Two registers are associated
with data transfer operations. The receive data regis-
ter, a read-only register, contains the output code of
the last valid DTMF tone pair to be decoded. The data
entered in the transmit data register determines which
tone pair is to be generated (see the Tone
Encoding/Decoding Table on page 3). Data can only
be written to the transmit data register. Transceiver
control is accomplished with two control registers (and
CRB) that occupy the same address space. A write
operation to CRB can be executed by setting the
appropriate bit in CRA. The following write operation to
the same address will then be directed to CRB, and
subsequent write cycles will then be redirected to
CRA. Internal reset circuitry clears the control registers
on powerup; however, as a precautionary measure,
the initialization software should include a routine to
clear the registers. Refer to the Actual Frequencies vs
Standard Requirements Table on page 5 and the
Control Register A Description below for details on the
control registers. The IRQ/CP pin can be programmed
to provide an interrupt request signal on validation of
DTMF signals, or when the transmitter is ready for
more data (burst mode only). The IRQ/CP pin is con-
figured as an open-drain output device and as such
requires a pullup resistor (see the Single-Ended Input
Configuration on page 2).
Control Register B Description
Bit Name Function Description
b0 BURST Burst mode A logic 0 enables the burst mode. When this mode is selected, data corresponding to the desired DTMF
tone pair can be written to the transmit data register, resulting in a tone burst of a specific duration (see
the 12 AC Characteristics on page 9). Subsequently, a pause of the same duration is induced.
Immediately following the pause, the status register is updated indicating that the transmit data regis-
ter is ready for further instructions, and an interrupt will be generated if the interrupt mode has been
enabled. Additionally, if call progress (CP) mode has bee enabled, the burst and pause duration is
increased by a factor of two. When the burst mode is not selected (logic 1), tone bursts of any desired
duration may be generated.
b1 TEST Test mode By enabling the test mode (logic 1), the IRQ/CP pin will present the delayed steering (inverted) signal
from the DTMF receiver. Refer to the Timing Diagrams on page 11 (b3 waveform) for details concerning
the output waveform.DTMF mode must be selected (CRA b1=0) before test mode can be implemented.
b2 S/D Single/dual tone A logic 0 will allow DTMF signals to be produced. If single-tone generation is enabled generation
(logic 1), either now or column tones (low or high group) can be generated depending on the state of
b3 in control register B.
b3 C/R Column/row tones When used in conjunction with b2 (above), the transmitter can be made to generate single-row or sin-
gle-column frequencies. A logic 0 will select row frequencies and a logic 1 will select column frequen-
cies.
