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M-8888-01T

P1-P3P4-P6P7-P9P10-P12P13-P14
Staus Register Description
Bit Name Status Flag Set Status Flag Cleared
b0 IRQ Interrupt has occurred. Bit one (b1) Interrupt is inactive. Cleared after
and/or bit 2 (b2) is set.status register is read.
b1 Transmit data register empty Pause duration has terminated and transmitter Cleared after status register is read or
(burst mode only) is ready for new data. when not in burst mode.
b2 Receive data register full. Valid data is in the receive data register. Cleared after status register is read.
b3 Delayed Steering Set on valid detection of the absence of a Cleared on detection of a valid DTMF
DTMF signal. signal.
b3 b2 b1 b0
RSEL IRQ CP/DTMF TOUT
M-8888
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7
Rev. 1
Common Crystal Connection
RS0 RD WR Function
0 1 0 Write to transmitter
0 0 1 Read from receiver
1 1 0 Write to control register
1 0 1 Read from status register
Internal Register Functions
CRA Bit Positions
b3 b2 b1 b0
C/R S/D TEST BURST
CRB Bit Positions
Equations
Application Circuit (Single-Ended Input)
DC Characteristics
Parameter Symbol Min Typ* Max Units
Operating supply voltage V
DD
4.75 5.0 5.25 V
Operating supply current I
DD
-1015mA
Power consumption P
O
- 50 78.75 mW
Inputs
High-level input voltage, OSC1 V
IHO
3.5 - - V
Low-level input voltage, OSC1 V
ILO
- - 1.5 V
Input impedance (@ 1 KHz), IN+, IN- R
IN
-10-MΩ
Steering threshold voltage V
TSt
2.2 2.3 2.5 V
Outputs
High-level output voltage (no load), OSC2 V
OHO
V
DD
- 0.1V - - V
Low-level output voltage (no load), OSC2 V
OLO
- - 0.1 V
Output leakage current (V
OH
= 2.4V), IRQ I
OZ
- 1.0 10.0 µA
V
REF
output voltage (no load) V
REF
2.4 - 2.7 V
V
REF
output resistance R
OR
- - 1.0 kΩ
Data Bus
Low-level input voltage V
IL
- - 0.8 V
High-level input voltage V
IH
2.0 - - V
Low-level output voltage (I
OL
= 1.6 mA) V
OL
- - 0.4 V
High-level output voltage (I
OH
= 400 µA) V
OH
2.4 - - V
Input leakage current (V
IN
= 0.4 to 2.4 V) I
IZ
- - 10.0 µA
All voltages referenced to V
SS
unless otherwise noted. V
DD
= 5.0 V ± 5%; f
C
= 3.579545 MHz; T
A
= -40°C to +85°C unless otherwise noted.
*Typical values are for use as design aids only, and are not guaranteed or subject to production testing.
Parameter Symbol Value
Power supply voltage
(V
DD
- V
SS
)V
DD
+ 6.0 V max
Voltage on any pin V
dc
V
SS
-0.3 V to V
DD
+ 0.3V
Current on any pin I
DD
10 mA max
Operating temperature T
A
-40°C to +85°C
Storage temperature T
S
-65°C to +150°C
Note: Exceeding these ratings may cause permanent damage. Functional operation under these
conditions is not implied.
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8
M-8888
Rev. 1
Absolute Maximum Ratings
Absolute Maximum Ratings are stress ratings. Stresses in
excess of these ratings can cause permanent damage to
the device. Functional operation of the device at these or
any other conditions beyond those indicated in the opera-
tional sections of this data sheet is not implied. Exposure of
the device to the absolute maximum ratings for an extend-
ed period may degrade the device and effect its reliability.
M-8888
www.clare.com
9
Rev. 1
AC Characteristics
Parameter Symbol Min Typ* Max Units
Receive signal conditions
Valid input signal levels - -29 - +1 dBm
(each tone of composite signal; Notes 1, 2, 3, 5, 6, 9) - 27.5 - 869 mV
RMS
Positive twist accept (Notes 2, 3, 6, 9) - - - 6 dB
Negative twist accept (Notes 2, 3, 6, 9) - - - 6 dB
Frequency deviation accept (Notes 2, 3, 5, 9) - ± 1.5% ± 2 Hz - - Nom.
Frequency deviation reject (Notes 2, 3, 5) - ± 3.5% - - Nom.
Third tone tolerance (Notes 2, 3, 4, 5, 9, 10) - - -16 - dB
Noise tolerance (Notes 2, 3, 4, 5, 7, 9, 10) - - -12 - dB
Dial tone tolerance (Notes 2, 3, 4, 5, 8, 9, 11) - - +22 - dB
Call progress
Lower frequency (@ -25 dBm) accept f
LA
- 320 - Hz
Upper frequency (@ -25 dBm) accept f
HA
- 510 - Hz
Lower frequency (@ -25 dBm) reject f
LR
- 290 - Hz
Upper frequency (@ -25 dBm) reject f
HR
- 540 - Hz
Receive timing
Tone present detect time t
DP
51114ms
Tone absent detect time t
DA
0.5 4 8.5 ms
Tone duration accept (the Timing Diagrams on page 10) t
REC
--40ms
Tone duration reject (the Timing Diagrams on page 10) t
REC
20 - - ms
Interdigit pause accept (the Timing Diagrams on page 10) t
ID
--40ms
Interdigit pause reject (the Timing Diagrams on page 10) t
DO
20 - - ms
Delay St to b3 t
PStb3
-13-µs
Delay St to RX
O
-RX
3
t
PStRX
-8-µs
Transmit timing
Tone burst duration (DTMF mode) t
BST
50 - 52 ms
Tone pause duration (DTMF mode) t
PS
50 - 52 ms
Tone burst duration (extended, call progress mode) t
BSTE
100 - 104 ms
Tone pause duration (extended, call progress mode) t
PSE
100 - 104 ms
Tone output
High group output level (R
L
= 10 KΩ)V
HOUT
-6.1 - -2.1 dBm
Low group output level (R
L
= 10 KΩ)V
LOUT
-8.1 - -4.1 dBm
Pre-emphasis (R
L
= 10 KΩ)dB
P
023dB
Output distortion (R
L
= 10 kΩ, 3.4 KHz bandwidth) THD - -25 - dB
Frequency deviation (f = 3.5795 MHz) f
D
- ± 0.7 ± 1.5 %
Output load resistance R
LT
10 - 50 kΩ
Microprocessor interface
RD, WR low pulse width t
CL
200 - - ns
RD, WR high pulse width t
CH
180 - - ns
RD, WR rise and fall time t
R
, t
F
--25ns
Address hold time t
AH
10 - - ns
Address setup time t
AS
23 - - ns
Data hold time (read) t
DHR
22 - - ns
RD to valid data delay (200 pF load) t
DDR
- - 150 ns
Data setup time (write) t
DSW
45 - - ns
Data hold time (write) t
DHW
10 - - ns
Input capacitance, D0-D3 C
IN
-5-pF
Output capacitance, IRQ /CP C/
OUT
-5-pF
P1-P3P4-P6P7-P9P10-P12P13-P14

M-8888-01T

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Description:
IC TRANSCEIVER DTMF CMOS 20-SOIC
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