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P5020NSE1QMB

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P5020 QorIQ Communications Processor Product Brief, Rev. 1
Features
Freescale Semiconductor28
Figure 8. Debug Architecture
Debug features include the following:
• Debug and performance monitoring registers in both the core and platform
— Accessible by target resident debug software and non-resident debug tools
— Capable of generating debug interrupts and trace event messages
• Run control with enhancements
— Classic
— Cross-core and SoC watchpoint triggering
• High speed trace port (Aurora-based)
— Supports Nexus class 2 instruction trace including timestamps
– Process id trace, watchpoint trace
— Supports “light” subset of Nexus class 3 data trace
– Enabled by cores, by event triggers, by Instruction Address Compare/Data Address
Compare events
— Data Acquisition Trace
– Compatible with Nexus class 3
– Instrumented code can generate data trace messages for values of interest
– Performed by writing values to control registers within each core
— Watchpoint Trace
– Can generate cross-core correlated breakpoints
– Breakpoint on any core can halt execution of selected additional cores with minimal skid
• CoreNet transaction analyzer
— Provides visibility to transactions across CoreNet (CoreNet fabric is otherwise transparent to
software)
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Events
Events
Events
Trac e
Scan
Trac e
SERDES
to Trace Probe
Tra c e
Tra c e
Transactions
Tra ce
Transactions
TLM TAP/SAP
SoC
Peripherals
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Performance
Monitor
TA P N ex us
Event
Processing
Unit
Performance
Nexus Port
Controller
Trace Buffers
CoreNet
Trac e
Analyzer
PCIe/sRIO
Memory
Controller
Aurora
Tra ce
Watchpoints
Monitor
CoreNet
Fabric
Developer Environment
P5020 QorIQ Communications Processor Product Brief, Rev. 1
Freescale Semiconductor 29
— Generates trace messages to Nexus Port Controller
— Supports filtering of accesses of interest
– Data Address Compare (4)
– Data Value Compare (2)
– Transaction Attribute Compare (2)
4 Developer Environment
Software developers creating solutions with the Power Architecture technology have long benefited from
a vibrant support ecosystem, including high quality tools, OSes, and network protocol stacks. Freescale is
working with our ecosystem partners to ensure that this remains the case for multicore, Power
Architecture-based products, including the P5020.
The various levels of the developer environment are shown in Figure 9, with the more broadly used tools
and boards at the base of the pyramid, and increasingly application-specific enablement items at the top.
Each level is described further, as follows:
• Section 4.1, “Base of the Pyramid: Broadly-Used Tools and Boards
• Section 4.2, “First Level of the Pyramid: Debug and Performance Analysis
• Section 4.3, “Second Level of the Pyramid: Simulation, Hypervisor, and DPAA Reference
“Stacklets”
• Section 4.4, “Top Level of the Pyramid: Application-Specific Enablement
Figure 9. Levels of Developer Environment
Hybrid Simulator
Hypervisor Micro-Kernel
DPAA Reference ‘Stacklets’
Advanced Debug Profiling
Hardware Platforms
SMP/AMP Capable OS’s
3rd Party Stacks
and Performance Analysis
Compilers, Debuggers, Bootloaders, LSPs, Drivers
Application-specific enablement items
Broadly-used tools and boards
P5020 QorIQ Communications Processor Product Brief, Rev. 1
Developer Environment
Freescale Semiconductor30
4.1 Base of the Pyramid: Broadly-Used Tools and Boards
4.1.1 Hardware Platforms
This category includes both development systems and the reference designs. Development systems are
available from both Freescale and our partners, with some partner systems being offered with form factors
and BOMs to support use as reference designs. Freescale development systems are supported by the open
source GNU tool set including compilers, linkers, and debuggers.
4.1.2 Compilers, Debuggers, Bootloaders, LSPs, Drivers
In active partnership with the open source community and Linux distribution and support suppliers, these
tools will be updated to fully and efficiently support the device.
4.1.3 SMP/AMP Capable OS’s
Open source tools will be part of an overall P5020 development board Linux support package, which will
include AMP and SMP versions of the Linux OS, and P5020 drivers for the accelerators and networking
and peripheral interfaces featured in the P5020. AMP Linux support will include the ability to boot
multiple instances of Linux on different cores. Power Architecture ecosystem partners are committed to
providing board support packages for the P5020.
4.2 First Level of the Pyramid: Debug and Performance Analysis
4.2.1 Advanced Debug
Advanced debug supports real-time trace analysis. It allows the developer to perform initial system
bring-up and development, and is required to deal with the special challenges of software debugging and
performance analysis in multicore systems.
4.2.2 Profiling and Performance Analysis
Freescale will bring tools support for profiling and performance analysis (such as enhanced statistics
gathering) to the market both by means of our CodeWarrior line of tools and in partnership with industry
standard tools suppliers.
4.3 Second Level of the Pyramid:
Simulation, Hypervisor, and DPAA Reference “Stacklets”
4.3.1 Hybrid Simulator
In conjunction with Virtutech, Freescale will provide a hybrid simulator that combines both functional and
performance measurement models of the P5020. The hybrid simulator allows the user to switch between
“fast functional mode” and “detailed performance mode” with capabilities that include the following:
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P5020NSE1QMB

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Buy P5020NSE1QMB
Manufacturer:
NXP / Freescale
Description:
Microprocessors - MPU StdTmpEnc 1600/1200
Lifecycle:
New from this manufacturer.
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