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P5020NSE1QMB

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Features
P5020 QorIQ Communications Processor Product Brief, Rev. 1
Freescale Semiconductor 7
• Two 4-channel DMA engines
3.3 P5020 Benefits
The P5020’s e5500 cores can be combined as a fully-symmetric, multi-processing, system-on-a-chip, or
they can be operated with varying degrees of independence to perform asymmetric multi-processing. Full
processor independence, including the ability to independently boot and reset each e5500 core, is a
defining characteristic of the device. The ability of the cores to run different operating systems, or run
OS-less, provides the user with significant flexibility in partitioning between control, datapath, and
applications processing. It also simplifies consolidation of functions previously spread across multiple
discrete processors onto a single device.
3.4 Data Path Acceleration Architecture (DPAA) Benefits
While the two Power Architecture cores offer a major leap in available processor performance in many
throughput-intensive, packet-processing networking applications, raw processing power is not enough to
achieve multi-Gbps data rates. To address this, the P5020 uses Freescale’s Data Path Acceleration
Architecture (DPAA) (see Section 3.9, “Data Path Acceleration Architecture (DPAA)”), which
significantly reduces data plane instructions per packet, enabling more CPU cycles to work on value-added
services rather than repetitive low-level tasks. Combined with specialized accelerators for cryptography
and pattern matching, the P5020 allows the user’s software to perform complex packet processing at high
data rates.
3.5 Critical Performance Parameters
The following table lists key performance indicators that define a set of values used to measure P5020
operation.
Table 1. P5020 Critical Performance Parameters
Indicator Values(s)
Top speed bin core
frequency
2.0 GHz
Maximum memory data
rate
1.3 GHz (DDR3/3L)
1
• 1.5-V for DDR3
• 1.35-V for DDR3L
Notes:
1
Conforms to JEDEC standard
Local bus • 3.3 V
• 2.5 V
•1.8V
Operating junction
temperature range
0–105 C
Package 1295-pin FC-PBGA (flip-chip plastic ball grid array)
P5020 QorIQ Communications Processor Product Brief, Rev. 1
Features
Freescale Semiconductor8
3.6 e5500 Core and Cache Memory Complex
Each e5500 is a superscalar dual issue processor, supporting out-of-order execution and in-order
completion, which allows the Power Architecture e5500 to perform more instructions per clock than other
RISC and CISC architectures.
3.6.1 e5500 Core Features
• Up to 2.0 GHz core clock speed
• 36 bit physical addressing
• 64 TLB SuperPages
• 512-entry, 4-Kbyte pages front end
• 3 Integer Units: 2 simple, 1 complex (integer multiply and divide)
• 64-byte cache line size
• L1 caches, running at same frequency of CPU
— 32-Kbyte Instruction, 8-way
— 32-Kbyte Data, 8-way
— Both with data and tag parity protection
• Supports data path acceleration architecture (DPAA) data and context “stashing” into the L1 data
cache and the backside L2 cache
• User, supervisor, and hypervisor instruction level privileges
• New processor facilities
— Hypervisor APU
— Classic double precision floating point unit
– Uses 32 64-bit floating-point registers (FPRs) for scalar single- and double-precision
floating-point arithmetic
– Replaces the embedded floating-point facility (SPE) implemented on the e500v1 and
e500v2
– Designed to comply with IEEE Std. 754™-1985 FPU for both single- and double-precision
operations
— “Decorated Storage” APU for improved statistics support
– Provides additional atomic operations, including a “fire-and-forget” atomic update of up to
two 64-bit quantities by a single access
— Expanded interrupt model
– Improved programmable interrupt controller (PIC) automatically ACKs interrupts
– Implements message send and receive functions for interprocessor communication,
including receive filtering
— External PID load and store facility
– Provides system software with an efficient means to move data and perform cache
operations between two disjoint address spaces
Features
P5020 QorIQ Communications Processor Product Brief, Rev. 1
Freescale Semiconductor 9
– Eliminates the need to copy data from a source context into a kernel context, change to
destination address space, then copy the data to the destination address space or alternatively
to map the user space into the kernel address space
3.6.2 512-Kbyte Private Backside Cache
• Each e5500 core features a 512-Kbyte private backside L2 cache running at the same frequency of
CPU. The caches support:Write Back, pseudo LRU replacement algorithm
• Tag parity and ECC data protection
• Eight-way, with arbitrary partitioning between instruction and data. For example, 3-ways
instruction, 5-ways data, and so on.
• Supports direct stashing of datapath architecture data into cache
3.6.3 CoreNet Platform Cache (CPC)
The QorIQ P5020 also contains 2x1-Mbyte of shared CoreNet platform cache, with the following features:
• Configurable as write back or write through
• Pseudo LRU replacement algorithm
• ECC protection
• 64-byte coherency granule
• Two cache line read 1024 bits per cycle at 800 MHz, 32-way cache array configurable to any of
several modes on a per-way basis
— Unified cache, I-only, D-only
— I/O stash (configurable portion of each packet copied to CPC on write to main memory)
– Stashing of all transactions and sizes supported
– Explicit (CoreNet signalled) and implicit (address range based) stash allocation
— Addressable SRAM (32-Kbyte granularity)
3.6.4 CoreNet Fabric and Address Map
The CoreNet fabric is Freescale’s next generation Interconnect Standard for multicore products, and
provides the following:
• A highly concurrent, fully cache coherent, multi-ported fabric
• Point-to-point connectivity with flexible protocol architecture allows for pipelined interconnection
between CPUs, platform caches, memory controllers, and I/O and accelerators at up to 800 MHz
• The CoreNet fabric has been designed to overcome bottlenecks associated with shared bus
architectures, particularly address issue and data bandwidth limitations. The P5020’s multiple,
parallel address paths allow for high address bandwidth, which is a key performance indicator for
large coherent multicore processors
• Eliminates address retries, triggered by CPUs being unable to snoop within the narrow snooping
window of a shared bus. This results in the device having lower average memory latency
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P5020NSE1QMB

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Buy P5020NSE1QMB
Manufacturer:
NXP / Freescale
Description:
Microprocessors - MPU StdTmpEnc 1600/1200
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