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P5020NSN1MMB

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Features
P5020 QorIQ Communications Processor Product Brief, Rev. 1
Freescale Semiconductor 13
• x8, x4, x2, and x1 link widths supported
• Both 32- and 64-bit addressing and 256-byte maximum payload size
• Full 64-bit decode with 36-bit wide windows
• Inbound INTx transactions
• Message Signaled Interrupt (MSI) transactions
3.8.2 Serial RapidIO
The Serial RapidIO interface is based on the RapidIO Interconnect Specification, Revision 1.3, with
features from 2.1. RapidIO is a high-performance, point-to-point, low-pin-count, packet-switched
system-level interconnect that can be used in a variety of applications as an open standard. The rich feature
set includes high data bandwidth, low-latency capability, and support for high-performance I/O devices as
well as message-passing and software-managed programming models. Receive and transmit ports operate
independently, and with 2 x 4 Serial RapidIO controllers, the aggregate theoretical bandwidth is 32 Gbps.
Key features of the Serial RapidIO interface unit include the following:
• Support for RapidIO Interconnect Specification, Revision 1.3 (all transaction flows and priorities)
• 1x, 2x, and 4x LP-serial link interfaces, with transmission rates of 2.5, 3.125, or 5.0 Gbaud (data
rates of 2.0, 2.5, or 4.0 Gbps) per lane.
• Auto-detection of 1x, 2x, or 4x mode operation during port initialization
• 34-bit addressing and up to 256-byte data payload
• Support for SWRITE, NWRITE, NWRITE_R and Atomic transactions
• Receiver-controlled flow control
• RapidIO error injection
• Internal LP-serial and application interface-level loopback modes
3.8.2.1 RapidIO Message Manager (RMan)
The key features of the RapidIO message manager (RMan) include the following:
• Manages two inbox/outbox mailboxes (queues) for data and one doorbell message structure
• Can multi-cast a single-segment 256-byte message to up to 32 different destination DevIDs
• Has four outbound segmentation units supporting RapidIO Type 5–6 and Type 8–11
3.8.3 Serial ATA (SATA) 2.0 Controllers
The key features of each of the two SATA include the following:
• Designed to comply with Serial ATA 2.6 Specification
• Supports host SATA I per spec Rev 1.0a
— OOB
— Port multipliers
—ATAPI 6+
P5020 QorIQ Communications Processor Product Brief, Rev. 1
Features
Freescale Semiconductor14
— Spread spectrum clocking on receive
• Support for SATA II extensions
— Asynchronous notification
— Hot plug including asynchronous signal recovery
— Link power management
— Native command queuing
— Staggered spin-up and port multiplier support
• Support for SATA I and II data rates (1.5 and 3.0 Gbaud)
• Standard ATA master-only emulation
• Includes ATA shadow registers
• Implements SATA superset registers (SError, SControl, SStatus)
• Interrupt driven
• Power management support
• Error handling and diagnostic features
— Far end/near end loopback
— Failed CRC error reporting
— Increased ALIGN insertion rates
— Scrambling and CONT override
3.9 Data Path Acceleration Architecture (DPAA)
The DPAA provides the infrastructure to support simplified sharing of networking interfaces and
accelerators by multiple CPU cores. These resources are abstracted into enqueue/dequeue operations by
means of a common DPAA Queue Manager (QMan) driver. Beyond enabling multicore resource sharing,
the DPAA significantly reduces software overheads associated with high-touch packet-forwarding
operations. Examples of the types of packet-processing services this architecture is optimized to support
are as follows:
• Traditional routing and bridging
•Firewall
• VPN termination for both IPsec and SSL VPNs
• Intrusion detection/prevention (IDS/IPS)
• Network anti-virus (AV)
The DPAA generally leaves software in control of protocol processing, while reducing CPU overheads
through off-load functions, which fall into two, broad categories:
• Packet Distribution and Queue/Congestion Management
• Accelerating Content Processing
Features
P5020 QorIQ Communications Processor Product Brief, Rev. 1
Freescale Semiconductor 15
3.9.1 Packet Distribution and Queue/Congestion Management
The following table lists some packet distribution and queue/congestion management offload functions.
3.9.2 Accelerating Content Processing
Properly implemented acceleration logic can provide significant performance advantages over most
optimized software with acceleration factors on the order of 10–100x. Accelerators in this category
typically touch most of the bytes of a packet (not just headers). To avoid consuming CPU cycles in order
to move data to the accelerators, these engines include well-pipelined DMAs. The following table lists
some specific content-processing accelerators on the P5020.
Table 2. Offload Functions
Function Type Definition
Data buffer
management
Supports allocation and deallocation of buffers belonging to pools originally created by software with
configurable depletion thresholds. Implemented in a module called the Buffer Manager (BMan).
Queue
management
Supports queuing and quality-of-service scheduling of frames to CPUs, network interfaces and DPAA logic
blocks, maintains packet ordering within flows. Implemented in a module called the Queue Manager
(QMan). The QMan, besides providing flow-level queuing, is also responsible for congestion management
functions such as RED/WRED, congestion notifications and tail discards.
Packet distribution Supports in-line packet parsing and general classification to enable policing and QoS-based packet
distribution to the CPUs for further processing of the packets. This function is implemented in the block
called the Frame Manager (FMan).
Policing Supports in-line rate-limiting by means of two-rate, three-color marking (RFC 2698). Up to 256 policing
profiles are supported. This function is also implemented in the FMan.
Table 3. Content-Processing Accelerators
Interface Definition
SEC 4.2 Crypto-acceleration for protocols such as IPsec, SSL, and 802.16
PME 2.1 Regex style pattern matching for unanchored searches, including cross-packet stateful patterns
Note: Prior versions of the SEC and PME are integrated into multiple members of the PowerQUICC and QorIQ family. Both of
these engines have been enhanced to work within the DPAA, and also upgraded in both features and performance.
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P5020NSN1MMB

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Microprocessors - MPU P5020 ST NE 1200/1200 R2
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