P5020 QorIQ Communications Processor Product Brief, Rev. 1
Features
Freescale Semiconductor6
– Supervisor
– Hypervisor
— Independent boot and reset
— Secure boot capability
• Two 1-Mbyte shared CoreNet platform cache (CPC)
• Hierarchical interconnect fabric
— CoreNet fabric supporting coherent and non-coherent transactions with prioritization and
bandwidth allocation amongst CoreNet end-points
— Queue manager fabric supporting packet-level queue management and quality of service
scheduling
• Two 64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving support
• Datapath acceleration architecture (DPAA) incorporating acceleration for the following functions:
— Packet parsing, classification, and distribution
— Queue management for scheduling, packet sequencing, and congestion management
— Hardware buffer management for buffer allocation and de-allocation
— Encryption/decryption (SEC 4.2)
— RegEx pattern matching (PME 2.1)
—RapidIO™ messaging manager (RMan)
— RAID5/6 Engine
– Support for XOR and Galois Field parity calculation
– Support for data protection information (DPI)
• Ethernet interfaces
— One 10 Gbps Ethernet (XAUI) controller
— Five 1 Gbps or four 2.5 Gbps Ethernet controllers
• High speed peripheral interfaces
— Four PCI Express 2.0 controllers/ports running at up to 5 GHz
— Two serial RapidIO 2.0 controllers/ports (version 1.3 with features of 2.1) running at up to 5
GHz with Type 11 messaging and Type 9 data streaming support
• Additional peripheral interfaces
— Dual SATA supporting 1.5 and 3.0 Gb/s operation
— Two USB 2.0 controllers with integrated PHY
— SD/MMC controller (eSDHC)
— Enhanced SPI controller
— Four I
2
C controllers
— Two Dual DUARTs
— Enhanced local bus controller (eLBC)
• 18 SerDes lanes to 5 GHz
• Multicore Programmable Interrupt Controller (MPIC)
