ADG5206/ADG5207 Data Sheet
Rev. A | Page 22 of 28
Figure 37. Break-Before-Make Time Delay, t
D
Figure 38. Charge Injection
Figure 39. Off Isolation
Figure 40. Channel-to-Channel Crosstalk
Figure 41. Bandwidth
3V
0V
OUTPUT
80% 80%
ADDRESS
DRIVE (V
IN
)
t
BBM
OUTPUT
ADG5206
1
50Ω
300Ω
GND
S1
S2 TO S15
S16
D
35pF
V
IN
3V EN
V
DD
V
SS
V
DD
V
SS
V
S
1
SIMILAR CONNECTION FOR ADG5207.
A0
A2
A1
A3
10714-035
3V
V
IN
V
OUT
Q
INJ
= C
L
× ΔV
OUT
ΔV
OUT
DSx
EN
GND
C
L
1nF
V
OUT
V
IN
R
S
V
S
V
DD
V
SS
V
DD
V
SS
A0
A1
A2
A3
ADG5206
1
1
SIMILAR CONNECTION FOR ADG5207.
0V
10714-037
V
OUT
50Ω
NETWORK
ANALYZER
R
L
50Ω
Sx
D
V
S
V
DD
V
SS
0.1µF
V
DD
0.1µF
V
SS
GND
50Ω
OFF ISOLATION = 20 log
V
OUT
V
S
10714-032
CHANNEL-TO-CHANNEL CROSSTALK = 20 log
V
OUT
GND
S1
D
S2
V
OUT
NETWORK
ANALYZER
R
L
50Ω
R
L
50Ω
V
S
V
S
V
DD
V
SS
0.1µF
V
DD
0.1µF
V
SS
10714-030
V
OUT
50Ω
NETWORK
ANALYZER
R
L
50Ω
Sx
D
INSERTION LOSS = 20 log
V
OUT
WITH SWITCH
V
OUT
WITHOUT SWITCH
V
S
V
DD
V
SS
0.1µF
V
DD
0.1µF
V
SS
GND
10714-033
Data Sheet ADG5206/ADG5207
Rev. A | Page 23 of 28
TERMINOLOGY
I
DD
I
DD
represents the positive supply current.
I
SS
I
SS
represents the negative supply current.
V
D
, V
S
V
D
and V
S
represent the analog voltage on Terminal D and
Terminal S, respectively.
R
ON
R
ON
is the ohmic resistance between Terminal D and
Terminal S.
∆R
ON
∆R
ON
represents the difference between the R
ON
of any two
channels.
R
FLAT (ON)
R
FLAT (ON)
is the flatness defined as the difference between the
maximum and the minimum value of on resistance measured
over the specified analog signal range.
I
S
(Off)
I
S
(Off) is the source leakage current with the switch off.
I
D
(Off)
I
D
(Off) is the drain leakage current with the switch off.
I
D
(On), I
S
(On)
I
D
(On) and I
S
(On) represent the channel leakage currents with
the switch on.
V
INL
V
INL
is the maximum input voltage for Logic 0.
V
INH
V
INH
is the minimum input voltage for Logic 1.
I
INL
, I
INH
I
INL
and I
INH
represent the low and high input currents of the
digital inputs.
C
D
(Off)
C
D
(Off) represents the off switch drain capacitance, which is
measured with reference to ground.
C
S
(Off)
C
S
(Off) represents the off switch source capacitance, which is
measured with reference to ground.
C
D
(On), C
S
(On)
C
D
(On) and C
S
(On) represent on switch capacitances, which
are measured with reference to ground.
C
IN
C
IN
represents digital input capacitance.
t
ON
(EN)
t
ON
(EN) represents the delay time between the 50% and 90%
points of the digital input and switch on condition.
t
OFF
(EN)
t
OFF
(EN) represents the delay time between the 50% and 90%
points of the digital input and switch off condition.
t
TRANSITION
t
TRANSITION
represents the delay time between the 50% and 90%
points of the digital inputs and the switch on condition when
switching from one address state to another.
Break-Before-Make Time Delay (t
D
)
t
D
represents the off time measured between the 80% point of
both switches when switching from one address state to another.
Off Isolation
Off isolation is a measure of unwanted signal coupling through
an off channel.
Charge Injection
Charge injection is a measure of the glitch impulse transferred
from the digital input to the analog output during switching.
Crosstalk
Crosstalk is a measure of unwanted signal that is coupled
through from one channel to another as a result of parasitic
capacitance.
Bandwidth
Bandwidth is the frequency at which the output is attenuated
by 3 dB.
On Response
On response is the frequency response of the on switch.
AC Power Supply Rejection Ratio (ACPSRR)
ACPSRR is a measure of the ability of a device to avoid coupling
noise and spurious signals that appear on the supply voltage pin to
the output of the switch. The dc voltage on the device is modulated
by a sine wave of 0.62 V p-p. The ratio of the amplitude of signal on
the output to the amplitude of the modulation is the ACPSRR.
ADG5206/ADG5207 Data Sheet
Rev. A | Page 24 of 28
APPLICATIONS INFORMATION
The ADG52xx family of switches and multiplexers provides a
robust solution for instrumentation, industrial, automotive,
aerospace, and other harsh environments that are prone to
latch-up, which is an undesirable high current state that can
lead to device failure and persist until the power supply is turned
off. The ADG5206/ADG5207 high voltage switches allow single-
supply operation from 9 V to 40 V and dual-supply operation
from ±9 V to ±22 V.
TRENCH ISOLATION
In the ADG5206/ADG5207, an insulating oxide layer (trench)
is placed between the NMOS and the PMOS transistors of each
CMOS switch. Parasitic junctions, which occur between the
transistors in junction isolated switches, are eliminated, and
the result is a completely latch-up proof switch.
In junction isolation, the N and P wells of the PMOS and NMOS
transistors form a diode that is reverse-biased under normal
operation. However, during overvoltage conditions, this diode
can become forward-biased. A silicon controlled rectifier (SCR)
type circuit is formed by the two transistors, causing a significant
amplification of the current that, in turn, leads to latch-up. With
trench isolation, this diode is removed and the result is a latch-
up proof switch.
Figure 42. Trench Isolation
NMOS PMOS
P WELL N WELL
BURIED OXIDE LAYER
HANDLE WAFER
TRENCH
10714-038

ADG5207BCPZ-RL7

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Multiplexer Switch ICs +12V +36V 8:1Mux
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union