Z87200
Zilog Spread-Spectrum Transceiver
4-53
Reducing the carrier frequency to 25% of the clock fre-
quency can reduce the distortion level, as shown in Figure
21. Although the distortion is still fairly severe, adequate
performance may be obtainable as a result of the system’s
processing gain, but the performance would be many dB
off the theoretical limit. As the PN chip rate of the system
increases, then so, too, does the effect of aliasing distor-
tion in the modulator, resulting in performance degrada-
tion. As a rule-of-thumb, one may restrict the I.F. frequency
to 25% of the clock frequency, but, in general, each appli-
cation and combination of PN chip rate, I.F. frequency, and
TXIFCLK/RXIFCLK frequency is unique and should be
evaluated before deciding whether to use the Z87200’s in-
ternal BPSK/QPSK modulator.
Figure 19. Spectrum of DDS Modulated at 0.4 x f
RXIFCLK
When Carrier Frequency is set to 0.25 x f
RXIFCLK
