ADDI9023 Data Sheet
Rev. 0 | Page 6 of 12
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1 2 3 4 5 6 7
1 2 3 4 5 6 7
A
B
C
D
E
F
G
A
B
C
D
E
F
G
ADDI9023
TOP VIEW
(Not to Scale)
VDD
SUBCK
XV9
XV4
XV8
XV1
XV2
XV5
XV3
XV7
VSS
VSS
VDREN
XSUBCK
VM
VMM
VL
VLL
VH
V1A
V6
V5
V4
V3B
V3A
V2B
V9
V2A
V8
V1B
V7
XSG1
XSG8
XSG7
XSG6
XSG5
XSG4
XSG3XSG2
XV6
10693-003
Figure 3. Pin Configuration
Table 5. Pin Function Descriptions
Pin No. Mnemonic Type
1
Description
A1 VM P V-Driver Midsupply.
A2 VL P V-Driver Low Supply.
A3 VH P V-Driver High Supply.
A4 VDREN DI V-Driver Enable. Active high.
A5 XSG8 DI Vertical Input.
A6 XSG5 DI Vertical Input.
A7 XSG6 DI Vertical Input.
B1 V8 VO2 CCD Vertical Transfer Clock.
B2 V7 VO2 CCD Vertical Transfer Clock.
B3 V9 VO2 CCD Vertical Transfer Clock.
B4 XSG7 DI Vertical Input.
B5 XSG2 DI Vertical Input.
B6 XSG3 DI Vertical Input.
B7 XSG4 DI Vertical Input.
C1 V6 VO2 CCD Vertical Transfer Clock.
C2 V5 VO3 CCD Vertical Transfer Clock (XV5 + XSG8).
C6 XV8 DI Vertical Input.
C7 XSG1 DI Vertical Input.
CCD Vertical Transfer Clock (XV4 + XSG7).
D2 V3B VO3 CCD Vertical Transfer Clock (XV3 + XSG6).
D6 XV7 DI Vertical Input.
D7 XV9 DI Vertical Input.
E1 V2B VO3 CCD Vertical Transfer Clock (XV2 + XSG4).
E2 V3A VO3 CCD Vertical Transfer Clock (XV3 + XSG5).
E6 XV5 DI Vertical Input.
E7 XV6 DI Vertical Input.
