8530DYI-01LF

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18

1©2015 Integrated Device Technology, Inc. Revision B, December 1, 2015

General Description

The 8530I-01is a low skew, 1-to-16 Differential- to-3.3V LVPECL

Fanout Buffer. The CLK, nCLK pair can accept most standard

differential input levels. The high gain differential amplifier accepts

peak-to-peak input voltages as small as 150mV as long as the

common mode voltage is within the specified minimum and

maximum range.

Guaranteed output and part-to-part skew characteristics make the

8530I-01 ideal for those clock distribution applications demanding

well defined performance and repeatability.

Features

• Sixteen differential 3.3V LVPECL output pairs

• CLK, nCLK input pair

• CLK, nCLK pair can accept the following differential input

levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL

• Maximum output frequency: 500MHz

• Translates any single-ended input signal to 3.3V LVPECL levels

with a resistor bias on nCLK input

• Output skew: 75ps (maximum)

• Additive phase jitter, RMS @ 106.25MHz: 0.162ps (typical)

• Full 3.3V supply voltage

• -40°C to 85°C ambient operating temperature

• Available in lead-free (RoHS 6) package

13 14 15 16 17 18 19 20 21 22 23 24

1

2

3

4

5

6

7

8

9

10

11

12

36

35

34

33

32

31

30

29

28

27

26

25

VCCO

Q11

nQ11

Q10

nQ10

V

EE

Q9

nQ9

Q8

nQ8

V

CCO

VCC

CLK

V

CCO

nQ0

Q0

nQ1

Q1

V

EE

nQ2

Q2

nQ3

Q3

V

CCO

VCC

VCCO

Q7

nQ7

Q6

nQ6

V

EE

Q5

nQ5

Q4

nQ4

V

CCO

48 47 46 45 44 43 42 41 40 39 38 37

VCCO

nQ12

Q12

nQ13

Q13

V

EE

nQ14

Q14

nQ15

Q15

V

CCO

nCLK

Pulldown

Pullup

Q15

nQ15

CLK0

nCLK0

Q14

Q13

Q12

nQ14

nQ13

nQ12

Q11

nQ11

Q10

Q9

Q8

nQ10

nQ9

nQ8

Q0

nQ0

Q1

Q2

Q3

nQ1

nQ2

nQ3

Q4

nQ4

Q5

Q6

Q7

nQ5

nQ6

nQ7

Block Diagram

Pin Assignment

8530I-01

48-Lead TQFP, E-Pad

7mm x 7mm x 1.0mm package body

Y Package

Top View

8530I-01

Datasheet

Low Skew, 1-to-16 Differential-to-3.3V

LVPECL Fanout Buffer

2©2015 Integrated Device Technology, Inc. Revision B, December 1, 2015

8530I-01 Datasheet

Pin Description and Pin Characteristic Tables

Table 1. Pin Descriptions

NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.

Table 2. Pin Characteristics

Number Name Type Description

1, 11, 14, 24, 25, 35, 38, 48 V

CCO

Power

Output power supply pins.

2, 3 Q11, nQ11 Output

Differential output pair. LVPECL interface levels.

4, 5 Q10, nQ10 Output

Differential output pair. LVPECL interface levels.

6, 19, 30, 43 V

EE

Power

Negative power supply pins.

7, 8 Q9, nQ9 Output

Differential output pair. LVPECL interface levels.

9, 10 Q8, nQ8 Output

Differential output pair. LVPECL interface levels.

12, 13 V

CC

Power

Positive power supply pins.

15, 16 Q7, nQ7 Output

Differential output pair. LVPECL interface levels.

17, 18 Q6, nQ6 Output

Differential output pair. LVPECL interface levels.

20, 21 Q5, nQ5 Output

Differential output pair. LVPECL interface levels.

22, 23 Q4, nQ4 Output

Differential output pair. LVPECL interface levels.

26, 27 Q3, nQ3 Output

Differential output pair. LVPECL interface levels.

28, 29 Q2, nQ2 Output

Differential output pair. LVPECL interface levels.

31, 32 Q1, nQ1 Output

Differential output pair. LVPECL interface levels.

33, 34 Q0, nQ0 Output

Differential output pair. LVPECL interface levels.

36 CLK Input Pulldown

Non-inverting differential clock input.

37 nCLK Input Pullup

Inverting differential clock input.

39, 40 Q15, nQ15 Output

Differential output pair. LVPECL interface levels.

41. 42 Q14, nQ14 Output

Differential output pair. LVPECL interface levels.

44, 45 Q13, nQ13 Output

Differential output pair. LVPECL interface levels.

46, 47 Q12, nQ12 Output

Differential output pair. LVPECL interface levels.

Symbol Parameter Test Conditions Minimum Typical Maximum Units

C

IN

Input Capacitance 4 pF

R

PULLUP

Input Pullup Resistor 51 k

R

PULLDOWN

Input Pulldown Resistor 51 k

3©2015 Integrated Device Technology, Inc. Revision B, December 1, 2015

8530I-01 Datasheet

Function Table

Table 3. Clock Input Function Table

NOTE 1: Refer to the Application Information section, Wiring the Differential Input to Accept single-ended Levels.

Absolute Maximum Ratings

NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.

These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond

those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for

extended periods may affect product reliability.

DC Electrical Characteristics

Table 4A. Power Supply DC Characteristics, V

CC

= V

CCO

= 3.3V ± 5%, V

EE

= 0V, T

A

= -40°C to 85°C

Inputs Outputs

Input to Output Mode PolarityCLK nCLK Q[0:15] nQ[0:15]

0 1 LOW HIGH Differential to Differential Non-Inverting

1 0 HIGH LOW Differential to Differential Non-Inverting

0 Biased; NOTE 1 LOW HIGH Single-Ended to Differential Non-Inverting

1 Biased; NOTE 1 HIGH LOW Single-Ended to Differential Non-Inverting

Biased; NOTE 1 0 HIGH LOW Single-Ended to Differential Inverting

Biased; NOTE 1 1 LOW HIGH Single-Ended to Differential Inverting

Item Rating

Supply Voltage, V

DD

4.6V

Inputs, V

I

-0.5V to V

CC

+ 0.5V

Outputs, I

O

Continuous Current

Surge Current

50mA

100mA

Package Thermal Impedance, 

JA

34.1°C/W (0 mps)

Storage Temperature, T

STG

-65C to 150C

Symbol Parameter Test Conditions Minimum Typical Maximum Units

V

CC

Positive Supply Voltage 3.135 3.3 3.465 V

V

CCO

Output Supply Voltage 3.135 3.3 3.465 V

I

EE

Power Supply Current 150 mA

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18

8530DYI-01LF

Mfr. #:

Buy 8530DYI-01LF

Manufacturer:

IDT

Description:

Clock Drivers & Distribution 16 LVPECL OUT BUFFER

Lifecycle:

New from this manufacturer.

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