4©2015 Integrated Device Technology, Inc. Revision B, December 1, 2015
8530I-01 Datasheet
Table 4B. Differential Input DC Characteristics, V
CC
= V
CCO
= 3.3V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
NOTE 1: V
IL
should not be less than -0.3V.
NOTE 2: Common mode input voltage is defined as V
IH.
Table 4C. LVPECL DC Characteristics, V
CC
= V
CCO
= 3.3V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
NOTE 1: Outputs terminated with 50 to V
CCO
– 2V.
AC Electrical Characteristics
Table 5. AC Electrical Characteristics, V
CC
= V
CCO
= 3.3V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. Device will meet specifications after thermal equilibrium has
been reached under these conditions.
NOTE: All parameters measured at 250MHz unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential cross
points.
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltage, same temperature, same frequency and
with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
I
IH
Input High Current
150 µA
A
I
IL
Input Low Current
-5 µA
-150 µA
V
PP
Peak-to-Peak Input Voltage; NOTE 1 0.15 1.3 V
V
CMR
Common Mode Input Voltage; NOTE 1, 2 V
EE
+ 0.5 V
CC
– 0.85 V
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
OH
Output High Voltage; NOTE 1 V
CCO
– 1.4 V
CCO
– 0.9 V
V
OL
Output Low Voltage; NOTE 1 V
CCO
– 2.0 V
CCO
– 1.7 V
V
SWING
Peak-to-Peak Output Voltage Swing 0.6 1.0 V
Symbol Parameter Test Conditions Minimum Typical Maximum Units
f
OUT
Output Frequency 500 MHz
t
JIT
Buffer Additive Phase Jitter,
RMS; refer to Additive Phase
Jitter Section
106.25MHz,
Integration Range: 12kHz – 20MHz
0.162 ps
212.5MHz,
Integration Range: 12kHz – 20MHz
0.152 ps
t
PD
Propagation Delay; NOTE 1 1 2 ns
tsk(o) Output Skew; NOTE 2, 3 75 ps
tsk(pp) Part-to-Part Skew; NOTE 2, 4 700 ps
odc Output Duty Cycle 47 53 %
t
R
/ t
F
Output Rise/ Fall Time 20% to 80% 300 700 ps
5©2015 Integrated Device Technology, Inc. Revision B, December 1, 2015
8530I-01 Datasheet
Additive Phase Jitter
The spectral purity in a band at a specific offset from the fundamental
compared to the power of the fundamental is called the dBc Phase
Noise. This value is normally expressed using a Phase noise plot
and is most often the specified plot in many applications. Phase
noise is defined as the ratio of the noise power present in a 1Hz band
at a specified offset from the fundamental frequency to the power
value of the fundamental. This ratio is expressed in decibels (dBm)
or a ratio of the power in the 1Hz band to the power in the
fundamental. When the required offset is specified, the phase noise
is called a dBc value, which simply means dBm at a specified offset
from the fundamental. By investigating jitter in the frequency domain,
we get a better understanding of its effects on the desired application
over the entire time record of the signal. It is mathematically possible
to calculate an expected bit error rate given a phase noise plot.
As with most timing specifications, phase noise measurements has
issues relating to the limitations of the equipment. Often the noise
floor of the equipment is higher than the noise floor of the device. This
is illustrated above. The device meets the noise floor of what is
shown, but can actually be lower. The phase noise is dependent on
the input source and measurement equipment.
Additive Phase Jitter @ 106.25MHz
12kHz to 20MHz = 0.162ps (typical)
SSB Phase Noise dBc/Hz
Offset from Carrier Frequency (Hz)
6©2015 Integrated Device Technology, Inc. Revision B, December 1, 2015
8530I-01 Datasheet
Parameter Measurement Information
LVPECL Output Load AC Test Circuit
Output Skew
Propagation Delay
Differential Input Level
Part-to-Part Skew
Output Rise/Fall Time
SCOPE
Qx
nQx
V
EE
V
CC,
2V
-1.3V ± -0.165V
V
CCO
nQx
Qx
nQy
Qy
t
PD
Q[0:15]
nQ[0:15]
CLK
nCLK
nCLK
CLK
V
CC
V
EE
V
CMR
Cross Points
V
PP
tsk(pp)
Part 1
Part 2
nQx
Qy
Qx
nQy
Q[0:15]
nQ[0:15]

8530DYI-01LF

Mfr. #:
Manufacturer:
IDT
Description:
Clock Drivers & Distribution 16 LVPECL OUT BUFFER
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet