7©2015 Integrated Device Technology, Inc. Revision B, December 1, 2015
8530I-01 Datasheet
Parameter Measurement Information, continued
Output Duty Cycle/Pulse Width/Period
Q[0:15]
nQ[0:15]
8©2015 Integrated Device Technology, Inc. Revision B, December 1, 2015
8530I-01 Datasheet
Applications Information
Recommendations for Unused Output Pins
Outputs:
LVPECL Outputs
All unused LVPECL outputs can be left floating. We recommend that
there is no trace attached. Both sides of the differential output pair
should either be left floating or terminated.
Wiring the Differential Input to Accept Single-Ended Levels
Figure 1 shows how a differential input can be wired to accept single
ended levels. The reference voltage V
REF
= V
CC
/2 is generated by
the bias resistors R1 and R2. The bypass capacitor (C1) is used to
help filter noise on the DC bias. This bias circuit should be located as
close to the input pin as possible. The ratio of R1 and R2 might need
to be adjusted to position the V
REF
in the center of the input voltage
swing. For example, if the input clock swing is 2.5V and V
CC
= 3.3V,
R1 and R2 value should be adjusted to set V
REF
at 1.25V. The values
below are for when both the single ended swing and V
CC
are at the
same voltage. This configuration requires that the sum of the output
impedance of the driver (Ro) and the series resistance (Rs) equals
the transmission line impedance. In addition, matched termination at
the input will attenuate the signal in half. This can be done in one of
two ways. First, R3 and R4 in parallel should equal the transmission
line impedance. For most 50 applications, R3 and R4 can be 100.
The values of the resistors can be increased to reduce the loading
for slower and weaker LVCMOS driver. When using single-ended
signaling, the noise rejection benefits of differential signaling are
reduced. Even though the differential input can handle full rail
LVCMOS signaling, it is recommended that the amplitude be
reduced. The datasheet specifies a lower differential amplitude,
however this only applies to differential signals. For single-ended
applications, the swing can be larger, however V
IL
cannot be less
than -0.3V and V
IH
cannot be more than V
CC
+ 0.3V. Though some
of the recommended components might not be used, the pads
should be placed in the layout. They can be utilized for debugging
purposes. The datasheet specifications are characterized and
guaranteed by using a differential signal.
Figure 1. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels
9©2015 Integrated Device Technology, Inc. Revision B, December 1, 2015
8530I-01 Datasheet
Differential Clock Input Interface
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and
other differential signals. Both signals must meet the V
PP
and V
CMR
input requirements. Figures 2A to 2F show interface examples for
the CLK /nCLK input driven by the most common driver types. The
input interfaces suggested here are examples only. Please consult
with the vendor of the driver component to confirm the driver
termination requirements. For example, in Figure 2A, the input
termination applies for IDT open emitter LVHSTL drivers. If you are
using an LVHSTL driver from another vendor, use their termination
recommendation.
Figure 2A. CLK/nCLK Input Driven by an
IDT Open Emitter LVHSTL Driver
Figure 2C. CLK/nCLK Input Driven by a
3.3V LVPECL Driver
Figure 2E. CLK/nCLK Input Driven by a
3.3V HCSL Driver
Figure 2B. CLK/nCLK Input Driven by a
3.3V LVPECL Driver
Figure 2D. CLK/nCLK Input Driven by a 3.3V LVDS
Driver
Figure 2F. CLK/nCLK Input Driven by a 2.5V SSTL
Driver
R1
50Ω
R2
50Ω
1.8V
Zo = 50Ω
Zo = 50Ω
CLK
nCLK
3.3V
LVHSTL
IDT
LVHSTL Driver
Differential
Input
H
*R
3
*
R4
C
L
K
n
C
L
K
3
.
3V
3
.
3V
Diff
e
r
e
nti
a
l
In
p
u
t
CLK
nCLK
Differential
Input
SSTL
2.5V
Zo = 60Ω
Zo = 60Ω
2.5V
3.3V
R1
120Ω
R2
120Ω
R3
120
Ω
R4
120
Ω

8530DYI-01LFT

Mfr. #:
Manufacturer:
IDT
Description:
Clock Drivers & Distribution 16 LVPECL OUT BUFFER
Lifecycle:
New from this manufacturer.
Delivery:
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