ADM1192 Data Sheet
VOLTAGE AND CURRENT READBACK
The ADM1192 contains the components to allow voltage and
current readback over an I
2
C bus. The voltage output of the
current sense amplifier and the voltage on the VCC pin are fed
into a 12-bit ADC via a multiplexer. The device can be instructed
to convert voltage and/or current at any time during operation
via an I
2
C command. When all conversions are complete, the
voltage and/or current values can be read back with 12-bit
accuracy in two or three bytes.
SERIAL BUS INTERFACE
Control of the ADM1192 is carried out via the serial system
management bus (I
2
C). This interface is compatible with the I
2
C
fast mode (400 kHz maximum). The ADM1192 is connected to
this bus as a slave device, under the control of a master device.
IDENTIFYING THE ADM1192 ON THE I
2
C BUS
The ADM1192 has a 7-bit serial bus slave address. When the
device powers up, it does so with a default serial bus address.
The five MSBs of the address are set to 01011; the two LSBs are
determined by the state of the ADR pin. There are four config-
urations available on the ADR pin that correspond to four I
2
C
addresses for the two LSBs (see Table 5). This scheme allows four
ADM1192 devices to operate on a single I
2
C bus.
GENERAL I
2
C TIMING
Figure 18 and Figure 19 show timing diagrams for general write
and read operations using the I
2
C. The I
2
C specification defines
conditions for different types of read and write operations, which
are discussed in the Write and Read Operations section. The
general I
2
C protocol operates as follows:
1. The master initiates a data transfer by establishing a start
condition, defined as a high-to-low transition on the serial
data line, SDA, while the serial clock line, SCL, remains
high. This indicates that a data stream is to follow. All slave
peripherals connected to the serial bus respond to the start
condition and shift in the next eight bits, consisting of a 7-bit
slave address (MSB first) plus an R/
W
bit that determines the
direction of the data transfer, that is, whether data is written to
or read from the slave device (0 = write, 1 = read).
The peripheral whose address corresponds to the transmitted
address responds by pulling the data line low during the
low period before the ninth clock pulse, known as the
acknowledge bit, and holding it low during the high period
of this clock pulse. All other devices on the bus now remain
idle while the selected device waits for data to be read from
it or written to it. If the R/
W
bit is 0, the master writes to
the slave device. If the R/
W
bit is 1, the master reads from
the slave device.
2. Data is sent over the serial bus in sequences of nine clock
pulses: eight bits of data followed by an acknowledge bit
from the slave device. Data transitions on the data line must
occur during the low period of the clock signal and remain
stable during the high period because a low-to-high transition
when the clock is high can be interpreted as a stop signal.
If the operation is a write operation, the first data byte after
the slave address is a command byte. This tells the slave
device what to expect next. It can be an instruction, such as
telling the slave device to expect a block write, or it can be
a register address that tells the slave where subsequent data
is to be written.
Because data can flow in only one direction, as defined by
the R/
W
bit, it is not possible to send a command to a slave
device during a read operation. Before performing a read
operation, it may be necessary to first execute a write
operation to tell the slave what sort of read operation to
expect and/or the address from which data is to be read.
3. When all data bytes are read or written, stop conditions are
established. In write mode, the master pulls the data line
high during the 10
th
clock pulse to assert a stop condition.
In read mode, the master device releases the SDA line
during the SCL low period before the ninth clock pulse,
but the slave device does not pull it low. This is known as a
no acknowledge. The master then takes the data line low
during the SCL low period before the 10
th
clock pulse, and
then high during the 10
th
clock pulse to assert a stop
condition.
Table 5. Setting I
2
C Addresses via the ADR Pin
Base Address ADR Pin State ADR Pin Logic State Address in Binary
1
Address in Hex
01011 Ground 00 0101100X 0x58
Resistor to ground 01 0101101X 0x5A
Floating 10 0101110X 0x5C
1
X = don’t care.
Rev. D | Page 10 of 20
