ADM1192-1ARMZ-R7 Datasheet ADM1192-1ARMZ-R7 | P13-P15

ADM1192 Data Sheet

WRITE AND READ OPERATIONS

The I

C specification defines several protocols for different

types of read and write operations. The operations used in the

ADM1192 are discussed in this section. Table 6 shows the

abbreviations used in the command diagrams (see Figure 21

to Figure 26).

Table 6. I

C Abbreviations

Abbreviation Condition

S Start

P Stop

R Read

W Write

A Acknowledge

N No acknowledge

QUICK COMMAND

The quick command operation allows the master to check if the

slave is present on the bus, as follows:

1. The master device asserts a start condition on SDA.

2. The master sends the 7-bit slave address, followed by the

write bit (low).

3. The addressed slave device asserts an acknowledge on SDA.

4. The master asserts a stop condition on SDA to end the

transaction.

05754-007

SLAVE

ADDRESS

1 2

Figure 21. Quick Command

WRITE COMMAND BYTE

In the write command byte operation, the master device sends

a command byte to the slave device, as follows:

1. The master device asserts a start condition on SDA.

2. The master sends the 7-bit slave address, followed by the

write bit (low).

3. The addressed slave device asserts an acknowledge on SDA.

4. The master sends the command byte. The command byte

is identified by an MSB = 0. An MSB = 1 indicates an

extended register write (see the Write Extended Command

Byte section).

5. The slave asserts an acknowledge on SDA.

6. The master asserts a stop condition on SDA to end the

transaction.

SLAVE

ADDRESS

W A

COMMAND

BYTE

A P

1 2 3 4 5 6

05754-008

Figure 22. Write Command Byte

The seven LSBs of the command byte are used to configure and

control the ADM1192. Tabl e 7 provides details of the function

of each bit.

Table 7. Command Byte Operations

Bit Default Name Function

C0 0 V_CONT

LSB, set to convert voltage continuously. If readback is attempted before the first conversion is complete,

the ADM1192 asserts an acknowledge and returns all 0s in the returned data.

C1 0 V_ONCE

Set to convert voltage once. Self-clears. I

C asserts a no acknowledge on attempted reads until the ADC

conversion is complete.

C2 0 I_CONT

Set to convert current continuously. If readback is attempted before the first conversion is complete, the

ADM1192 asserts an acknowledge and returns all 0s in the returned data.

C3 0 I_ONCE

Set to convert current once. Self-clears. I

C asserts a no acknowledge on attempted reads until the ADC

conversion is complete.

C4 0 VRANGE

Selects different internal attenuation resistor networks for voltage readback. A 0 in C4 selects a 14:1

voltage divider. A 1 in C4 selects a 7:2 voltage divider. With an ADC full scale of 1.902 V, the voltage at the

VCC pin for an ADC full-scale result is 26.52 V for VRANGE = 0 and 6.65 V for VRANGE = 1.

Not applicable

Unused.

C6 0 STATUS_RD

Status Read. When this bit is set, the data byte read back from the ADM1192 is the status byte. This

contains the status of the device alerts. See Table 15 for full details of the status byte.

Rev. D | Page 12 of 20

Data Sheet ADM1192

WRITE EXTENDED COMMAND BYTE

In the write extended command byte operation, the master

device writes to one of the three extended registers of the slave

device, as follows:

1. The master device asserts a start condition on SDA.

2. The master sends the 7-bit slave address, followed by the

write bit (low).

3. The addressed slave device asserts an acknowledge on SDA.

4. The master sends the register address byte. The MSB of this

byte is set to 1 to indicate an extended register write. The two

LSBs indicate which of the three extended registers are to be

written to (see Table 8). All other bits should be set to 0.

5. The slave asserts an acknowledge on SDA.

6. The master sends the extended command byte (refer to

Table 9, Table 10, and Table 11).

7. The slave asserts an acknowledge on SDA.

8. The master asserts a stop condition on SDA to end the

transaction.

SLAVE

ADDRESS

W A

ADDRESS

EXTENDED

COMMAND

BYTE

1 2

4 5

6 7

05754-009

Figure 23. Write Extended Byte

Table 9, Table 10, and Table 11 provide the details of each

extended register.

Table 8. Extended Register Addresses

A6 A5 A4 A3 A2 A1 A0 Extended Register

0 0 0 0 0 0 1 ALERT_EN

0 0 0 0 0 1 0 ALERT_TH

0 0 0 0 0 1 1 CONTROL

Table 9. ALERT_EN Register Operations

Bit Default Name Function

0 0 EN_ADC_OC1 LSB, enabled if a single ADC conversion on the I channel exceeds the threshold set in the ALERT_TH register.

1 0 EN_ADC_OC4

Enabled if four consecutive ADC conversions on the I channel exceed the threshold set in the

ALERT_TH register.

2 1 EN_OC_ALERT

Enables the OC_ALERT register. If an overcurrent condition is present compared to the SETV threshold, and

the TIMER pin charges to 1.3 V, the OC_ALERT register captures and latches this condition.

EN_OFF_ALERT

Enables an alert if the hot swap operation is turned off by an operation that writes the SWOFF bit high.

This allows a software override of the ALERT output and turns on a P-channel FET controlled by ALERT.

4 0 CLEAR

Clears the OC_ALERT and ADC_ALERT status bits in the status register. The value of these bits can

immediately change if the source of the alert is not cleared and the alert function is not disabled.

The CLEAR bit self-clears to 0 after the STATUS register bits are cleared.

Table 10. ALERT_TH Register Operations

Bit Default Function

[7:0] FF

The ALERT_TH register sets the current level at which an alert occurs. Defaults to ADC full scale. The ALERT_TH 8-bit

value corresponds to the top eight bits of the current channel data.

Table 11. CONTROL Register Operations

Bit Default Name Function

SWOFF LSB, forces the ALERT pin to deassert. Can be active only if the EN_OFF_ALERT bit is high (see Table 9).

Rev. D | Page 13 of 20

ADM1192 Data Sheet

READ VOLTAGE AND/OR CURRENT DATA BYTES

Depending on how the device is configured, the ADM1192 can

be set up to provide information in three ways after a conversion

(or conversions): voltage and current readback, voltage only

readback, and current only read back. See the Write Command

Byte section for more details.

Voltage and Current Readback

The ADM1192 digitizes both voltage and current. Three bytes

are read back in the format shown in Table 12.

Table 12. Voltage and Current Readback Format

Byte Contents B7 B6 B5 B4 B3 B2 B1 B0

Voltage

MSBs

V11 V10 V9 V8 V7 V6 V5 V4

Current

MSBs

I11 I10 I9 I8 I7 I6 I5 I4

LSBs

Voltage Readback

The ADM1192 digitizes voltage only. Two bytes are read back in

the format shown in Tabl e 13.

Table 13. Voltage Only Readback Format

Byte

Contents B7 B6 B5 B4 B3 B2 B1 B0

Voltage MSBs

V11

V10

2 Voltage LSBs V3 V2 V1 V0 0 0 0 0

Current Readback

The ADM1192 digitizes current only. Two bytes are read back

in the format shown in Table 14.

Table 14. Current Only Readback Format

Byte

Contents B7 B6 B5 B4 B3 B2 B1 B0

Current MSBs

I11 I10 I9 I8 I7 I6 I5 I4

2 Current LSBs I3 I2 I1 I0 0 0 0 0

The following series of events occurs when the master receives

three bytes (voltage and current data) from the slave device:

1. The master device asserts a start condition on SDA.

2. The master sends the 7-bit slave address, followed by the

read bit (high).

3. The addressed slave device asserts an acknowledge on SDA.

4. The master receives the first data byte.

5. The master asserts an acknowledge on SDA.

6. The master receives the second data byte.

7. The master asserts an acknowledge on SDA.

8. The master receives the third data byte.

9. The master asserts a no acknowledge on SDA.

10. The master asserts a stop condition on SDA, and the

transaction ends.

For cases where the master is reading voltage only or current

only, two data bytes are read and Step 7 and Step 8 are not required.

SLAVE

ADDRESS

R A DATA 1 DATA 2

N PDATA 3AA

1 2

3 4 5 6 7 8 9 10

05754-010

Figure 24. Three-Byte Read from ADM1192

SLAVE

ADDRESS

R A

DATA 1

N P

DATA 2A

1 2 3 4 5 6 7 8

05754-011

Figure 25. Two-Byte Read from ADM1192

Converting ADC Codes to Voltage and Current Readings

Equation 1 and Equation 2 can be used to convert ADC codes

representing voltage and current from the ADM1175 12-bit

ADC into actual voltage and current values.

Voltage = (V

FULLSCALE

/4096) × Code (1)

where:

FULLSCALE

= 6.65 V (7:2 range) or 26.52 V (14:1 range).

Code is the ADC voltage code read from the device

(Bit V11 to Bit V0).

Current = ((I

FULLSCALE

/4096) × Code)/Sense Resistor (2)

where:

FULLSCALE

= 105.84 mV.

Code is the ADC current code read from the device

(Bit I11 to Bit I0).

Read Status Register

A single register of status data can also be read from the

ADM1192 as follows:

1. The master device asserts a start condition on SDA.

2. The master sends the 7-bit slave address, followed by the

read bit (high).

3. The addressed slave device asserts an acknowledge on SDA.

4. The master receives the status byte.

5. The master asserts an acknowledge on SDA.

05754-012

SLAVE

ADDRESS

STATUS

BYTE

R A A

1 2 3 4 5

Figure 26. Status Read from ADM1192

Table 15 shows the ADM1192 STATUS registers in detail. Note

that Bit 1, Bit 3, and Bit 5 are cleared by writing to Bit 4 (the

CLEAR bit) of the ALERT_EN register.

Rev. D | Page 14 of 20

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ADM1192-1ARMZ-R7

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