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74LVTH16652MTD

P1-P3P4-P6P7-P9
© 2000 Fairchild Semiconductor Corporation DS012024 www.fairchildsemi.com
January 2000
Revised November 2000
74LVTH16652 Low Voltage 16-Bit Transceiver/Register with 3-STATE Outputs
74LVTH16652
Low Voltage 16-Bit Transceiver/Register
with 3-STATE Outputs
General Description
The LVTH16652 consists of sixteen bus transceiver circuits
with D-type flip-flops, and control circuitry arranged for mul-
tiplexed transmission of data directly from the input bus or
from the internal registers. Each byte has separate control
inputs which can be shorted together for full 16-bit opera-
tion. Data on the A or B bus will be clocked into the regis-
ters as the appropriate clock pin goes to the HIGH logic
level. Output Enable pins (OEAB, OEBA
) are provided to
control the transceiver function (see Functional Descrip-
tion).
The LVTH16652 data inputs include bushold, eliminating
the need for external pull-up resistors to hold unused
inputs.
The transceivers are designed for low-voltage (3.3V) V
CC
applications, but with the capability to provide a TTL inter-
face to a 5V environment. The LVTH16652 is fabricated
with an advanced BiCMOS technology to achieve high
speed operation similar to 5V ABT while maintaining low
power dissipation.
Features
■ Input and output interface capability to systems at
5V V
CC
■ Bushold data inputs eliminate the need for external
pull-up resistors to hold unused inputs
■ Live insertion/extraction permitted
■ Power Up/Down high impedance provides glitch-free
bus loading
■ Outputs source/sink
−32 mA/+64 mA
■ Functionally compatible with the 74 series 16652
■ Latch-up performance exceeds 500 mA
■ ESD performance:
Human-body model
> 2000V
Machine model
> 200V
Charged-device model
> 1000V
Ordering Code:
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Order Number Package Number Package Description
74LVTH16652MEA MS56A 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide
74LVTH16652MTD MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
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74LVTH16652
Connection Diagram Pin Descriptions
Truth Table
(Note 1)
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial = LOW-to-HIGH Clock Transition
Note 1: The data output functions may be enabled or disabled by various signals at OEAB or OEBA
inputs. Data input functions are always enabled, i.e.,
data at the bus pins will be stored on every LOW-to-HIGH transition on the clock inputs. This also applies to data I/O (A and B: 8–15) and #2 control pins
Pin Names Description
A
0
–A
15
Data Register A Inputs/
3-STATE Outputs
B
0
–B
15
Data Register B Inputs/
3-STATE Outputs
CPAB
n
, CPBA
n
Clock Pulse Inputs
SAB
n
, SBA
n
Select Inputs
OEAB
n
, OEBA
n
Output Enable Inputs
Inputs Inputs/Outputs Operating Mode
OEAB
1
OEBA
1
CPAB
1
CPBA
1
SAB
1
SBA
1
A
0
thru A
7
B
0
thru B
7
L H H or L H or L X X Input Input Isolation
LH
X X Store A and B Data
XH
H or L X X Input Not Specified Store A, Hold B
HH
X X Input Output Store A in Both Registers
LXH or L
X X Not Specified Input Hold A, Store B
LL
X X Output Input Store B in Both Registers
L L X X X L Output Input Real-Time B Data to A Bus
L L X H or L X H Store B Data to A Bus
H H X X L X Input Output Real-Time A Data to B Bus
H H H or L X H X Stored A Data to B Bus
H L H or L H or L H H Output Output Stored A Data to B Bus and
Stored B Data to A Bus
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74LVTH16652
Logic Diagrams
Please note that these diagrams are provided only for the understanding of logic operations and should not be used to estimate propagation delays.
P1-P3P4-P6P7-P9

74LVTH16652MTD

Mfr. #:
Buy 74LVTH16652MTD
Manufacturer:
ON Semiconductor
Description:
IC TXRX NON-INVERT 3.6V 56TSSOP
Lifecycle:
New from this manufacturer.
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