5
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POWER MANAGEMENT
SC2677B
EXPEXP
EXPEXP
EXP
ANDED PIN DESCRIPTIONANDED PIN DESCRIPTION
ANDED PIN DESCRIPTIONANDED PIN DESCRIPTION
ANDED PIN DESCRIPTION
Pin 1Pin 1
Pin 1Pin 1
Pin 1
, 2, 2
, 2, 2
, 2
4:4:
4:4:
4: (CS2+, CS1+)
Current sense amplifier (for OCP protection) non-inverting
inputs.
Pin 2, 23:Pin 2, 23:
Pin 2, 23:Pin 2, 23:
Pin 2, 23: (CS2-, CS1-)
Current sense amplifier (for OCP protection) inverting
inputs.
Pin 3:Pin 3:
Pin 3:Pin 3:
Pin 3: (VREF)
Internal 0.5V reference. Connected to the + input of the
master channel error amplifier.
Pin 4: Pin 4:
Pin 4: Pin 4:
Pin 4: (FREQ)
External frequency adjustment. Connect a resistor to
AGND to set the switching frequency. Please see more
information in Application section.
Pin 5: Pin 5:
Pin 5: Pin 5:
Pin 5: (VCC)
Bias pin for the controller. Connect a ceramic decoupling
capacitor from this pin to AGND with minimum trace
length.
Pin 6: Pin 6:
Pin 6: Pin 6:
Pin 6: (+IN2)
“+” input of the slave error amplifier.
Pin 7, 18: Pin 7, 18:
Pin 7, 18: Pin 7, 18:
Pin 7, 18: (-IN2, -IN1)
“-” inputs of the error amplifiers.
Pin 8, 1Pin 8, 1
Pin 8, 1Pin 8, 1
Pin 8, 1
77
77
7
::
::
: (COMP2, COMP1)
Compensation pins of the error amplifiers.
Pin 9, 1Pin 9, 1
Pin 9, 1Pin 9, 1
Pin 9, 1
6: 6:
6: 6:
6: (BST2, BST1)
Supply pins for the high side drivers. Usually connected
to bootstrap circuit.
Pin 1Pin 1
Pin 1Pin 1
Pin 1
0, 10, 1
0, 10, 1
0, 1
5:5:
5:5:
5: (DH2, DH1)
Gate drive pins for the top MOSFETs. Requires a small
series resistor.
Pin 1Pin 1
Pin 1Pin 1
Pin 1
11
11
1
, 1, 1
, 1, 1
, 1
4:4:
4:4:
4: (DL2, DL1)
Gate drive pins for the bottom MOSFETs. Requires a
small series resistor.
Pin 12:Pin 12:
Pin 12:Pin 12:
Pin 12: (PGND)
Power GND. Return of the high side and low side gate
drivers.
Pin 1Pin 1
Pin 1Pin 1
Pin 1
3:3:
3:3:
3: (BSTC)
Supply pin for bottom MOSFET gate drivers.
Pin 19: Pin 19:
Pin 19: Pin 19:
Pin 19: (PHASING)
This pin controls the phase shift between master and
slave for optimum noise immunity. Use a resistive
divider from the FREQ pin (pin 2) to AGND, and connect
the tap of the resistive divider to pin 17. Please see
more information in Application section.
Pin 20:Pin 20:
Pin 20:Pin 20:
Pin 20: (SS/ENA)
Soft start pin. Connect a ceramic capacitor from this pin
to AGND, and there is an internal current source charg-
ing up this capacitor during soft start. The PWM opera-
tion can be disabled if this pin is pulled low.
Pin 2Pin 2
Pin 2Pin 2
Pin 2
1:1:
1:1:
1: (PWRGD)
Power good signal. This is an open collector output. It is
pulled low internally if output voltage is outside the
power good window.
Pin 22:Pin 22:
Pin 22:Pin 22:
Pin 22: (GND)
Analog GND. Return of the analog signals and bias of
the chip.
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Notes:Notes:
Notes:Notes:
Notes:
(1) Only available in tape and reel packaging. A reel con-
tains 2500 devices.
(2) Lead free package. Device is fully WEEE and RoHS
compliant.
Top View
(TSSOP-24 Pin)
Pin Configuration Ordering Information
Pin Descriptions
