SC2677BTETRT Datasheet SC2677BTETRT | P7-P9

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POWER MANAGEMENT

SC2677B

Main Loop(s)Main Loop(s)

Main Loop(s)

The SC2677B is a dual, voltage mode synchronous Buck

controller. The two separate channels are identical and

share only IC supply pins (Vcc and GND), output driver

ground (PGND) and pre-driver supply voltage (BSTC). They

also share a common oscillator generating a sawtooth

waveform for channel 1 and an dephased sawtooth for

channel 2. Channel 2 has both inputs of the error ampli-

fier uncommitted and available externally. This allows the

SC2677B to operate in two distinct modes.

a) Two independent channels with either common

or different input voltages and different output

voltages. The two channels each have their own volt-

age feedback path from their own output. In this

mode, positive input of the error amplifier 2 is con-

nected externally to Vref. If the application uses a

common input voltage, the sawtooth phase shift be-

tween the channels provides some measure of input

ripple current cancellation.

b) Two channels operating in current sharing mode

with common output voltage and either common in-

put voltage or different input voltages. In this mode,

channel 1 operates as a voltage mode Buck controller,

as before, but error amplifier 2 monitors and ampli-

fies the difference in voltage across the output cur-

rent sense resistors of channel 1 and channel 2 (Mas-

ter and Slave) and adjusts the Slave duty cycle to

match output currents. To controller also works well

for using the output choke winding resistance as cur-

rent sensing element (please refer the application

schematic for details). The amount of the current of

the slave channel vs the master channel can be pro-

grammed according to the application. This feature

is especially useful when two input sources are used

and each source has its power budget.

The offset of the current sharing error amplifier is

trimmed whthin the range of -2mV to 0mV. The po-

larity being such that the slave is OFF if the master

has no current.

Power GoodPower Good

Power Good

The controller provides a power good signal. This is an

open collector output, which is pulled low if the output

voltage is outside of the power good window.

SofSof

Sof

t Start Star

t Star

t/Enablet/Enable

t/Enable

The Soft Start/Enable (SS/ENA) pin serves several

functions. If held below the Enable threshold, both chan-

nels are inhibited. DH1 and DH2 will be low, turning off

the top FETs. Between the Soft Start Enable threshold

and the Soft Start End threshold, the duty cycle is allowed

to increase. At the Soft Start End threshold, maximum

duty cycle is reached. In practical applications the error

amplifier will be controlling the duty cycle before the Soft

Start End threshold is reached. To avoid boost problems

during start-up in current share mode, both channels start

up in asynchronous mode, and the bottom FET body diode

is used for circulating current during the top FET off time.

When the SS/ENA pin reaches the Soft Start Transition

threshold, the channels begin operating in synchronous

mode for improved efficiency. The soft start pin sources

approximately 50uA and soft start timing can be set by

selection of an appropriate soft start capacitor value.

reqreq

req

uency Seuency Se

uency Se

t and Phasingt and Phasing

t and Phasing

The switching frequency can be programmed by connect-

ing a resistor from the FREQ pin to AGND. The PHASING

pin controls the phase shift between the master sawtooth

and slave sawtooth which allows the adjustment of the

phase shift for maximum noise immunity by controlling

the timing between master and slave transition. A resis-

tive divider is used from the FREQ pin to AGND and the

divided voltage is fed to the PHASING pin as depicted.

SC2677B

12 13

2 23

VREF

FREQ

VCC

+IN2

-IN2

COMP2

BST2

DH2

DL2

PGND BSTC

GND

PWRGD

SS/ENA

PHASING

-IN1

COMP1

BST1

DH1

DL1

CS2+

CS2- CS1-

CS1+

R13

R19

Application Information

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POWER MANAGEMENT

SC2677B

Over Current ProtectionOver Current Protection

Over Current Protection

Current sense amplifiers sense the inductor DCR, and com-

pare with an internal OCP reference. As over current being

detected, the current sense amplifier will trip the peak

current limit on cycle-by-cycle basis. If the over current

condition sustains, and the output voltage drops below

75% of its nominal voltage level, the PWM will be disabled

and the power supply be latched off with short amount of

delay. The latch can be reset by power cycling.

(R13+R19) vs.Oscillator Frequency

300

400

500

600

700

800

900

1000

4 6 8 101214161820

(R13+R19) (kohm)

Oscillator Frequency (kHz)

Vphasing vs Phase Shift

100

120

140

160

180

0.55 0.60 0.65 0.70 0.75 0.80 0.85 0.90

Vphasing (V)

Phase (deg)

Controller Power DissipationController Power Dissipation

Controller Power Dissipation

Controller power dissipation is generated by following

parameter; switching frequency, total gate charge of all

selected MOSFETs and supply voltage.

= Vin * (I

+ Q

* F

)

= Q

* N

Where

Vin

: Supply voltage for controller and driving

MOSFET.

Layout GuidelinesLayout Guidelines

Layout Guidelines

Power and signal traces must be kept separated for noise

considerations. Feedback, current sense traces and ana-

log ground should not cross any traces or planes carrying

high switching currents, such as in the input loop or the

phase node.

The input loop, consisting of the input capacitors and both

MOSFETs must be kept as small as possible. Since all of

the high switching currents occur in the input loop, the

enclosed loop area must be kept small to minimize induc-

tance and radiated and conducted noise emissions.

An example is shown below to demonstrate the

procedure introduced above.

Vin =12V

Fsw =250KHz

N =4(number of MOSFET)

Then

= 108nC

= 27nC (per MOSFET)

It’s recommended that the below figure be performed to

ensure SC2677B under safe operation area.

: Supply current for controller.

: Total gate charge of all selected MOSFETs.

: Total gate charge of per selected MOSFETs.

: Switching frequency.

: Number of MOSFET.

limitation (with loading)

100

140

180

220

260

300

340

380

420

460

500

540

580

620

150 200 250 300 350 400 450 500

Fsw(KHz)

(nC)

5Vin

8.5Vin

12Vin

SOA

Application Information(Cont.)

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POWER MANAGEMENT

SC2677B

Designing for minimum trace length is not the only factor

for best design, often a optimum layout can be achieved

by keeping the wide trace and using proper layer stacking

to minimize the stray inductance.

It is important to keep the gate traces short, the IC must

be close to the power switches. It is recommended to use

at least 25 mil width or wider trace when. A good place-

ment can help if the controller is placed in the middle of

the two PWM channels.

Grounding requirements are always important in a buck

converter layout, especially at high power. Power ground

(PGND) should be returned to the bottom MOSFET source

to provide the best gate current return path. Analog ground

(AGND) should be used for the anaglog returns such as

chip decoupling, frequency setiing, reference voltage (or

soft starting cap), and the compensation.

This AGND shape should be single point connected to the

PGND shape near the ground side of the output capacitors.

This will provide noise free analog ground for operation

stablity, and also provide best possible remote sensing for

the feedback voltage.

In case two output rails need to be regulated, the AGND

shape should single point connected to the geometric cen-

ter of the PGND for the two point of loads. The single

ponit tie is a must to prevent the power current from flow-

ing on the AGND shape, so that the analog circuitry in the

controller has an electrically quiet reference and to pro-

vide the greatest noise free operation. Keep in mind that

the AGND pin is never allowed to have bigger than 1V

voltage difference vs the PGND pin. This usually achiev-

able by using a ground plane for PGND in PCB layout.

Using ground plane for PGND can reduce the physical sepa-

ration between the two grounds, such that even the fast

current transitions in the PGND plane can not generate

voltage spikes exceeding the 1V level, therefore prevent-

ing unstable and erratic behavior from happening.

The feedback divider must be close to the IC and be re-

turned to analog ground. Current sense traces must be

run parallel and close to each other and to analog ground.

Application Information(Cont.)

The IC must have a ceramic decoupling capacitor across

its supply pins, mounted as close to the device as possible.

The small ceramic, noise-filtering capacitors on the cur-

rent sense lines should also be placed as close to the IC as

possible.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P19

SC2677BTETRT

Mfr. #:

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Description:

Switching Controllers DUAL SYNCH VOLT MODE CONTROLLR

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