AX5042
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CIRCUIT DESCRIPTION
The AX5042 is a true single chip low−power CMOS
transceiver primarily for use in SRD bands. The on−chip
transceiver consists of a fully integrated RF front−end with
modulator and demodulator. Base band data processing is
implemented in an advanced and flexible communication
controller that enables user friendly communication via the
SPI interface or in direct wire mode.
AX5042 can be operated from 2.3 V to 2.8 V power
supply over a temperature range from −40°C to 85°C, it
consumes 13 − 37 mA for transmitting depending on data
mode and output power and 17 − 23 mA for receiving.
The AX5042 features make it an ideal interface for
integration into various battery powered SRD solutions such
as ticketing or as transceiver for telemetric applications e.g.
in sensors. As primary application, the transceiver is
intended for UHF radio equipment in accordance with the
European Telecommunication Standard Institute (ETSI)
specification EN 300 220−1 and the US Federal
Communications Commission (FCC) standard CFR47, part
15. The use of AX5042 in accordance to FCC Par 15.247,
allows for improved range in the 915 MHz band.
Additionally AX5042 is compatible with the low frequency
standards of 802.15.4 (ZigBee).
The AX5042 can be operated in two fundamentally
different modes.
In wire mode the IC behaves as an extension of any wire.
The internal communication controller is disabled and the
modem data is directly available on a dedicated pin (DATA).
The bit clock is also output on a dedicated pin (DCLK). In
this mode the user can connect the data pin to any port of a
micro−controller or to a UART, but has to control coding,
checksums, pre and post ambles. The user can choose
between synchronous and asynchronous wire mode,
asynchronous wire mode performs RS232 start bit
recognition and re−synchronization for transmit.
In frame mode data is sent and received via the SPI port
in frames. Pre− and postambles as well as checksums can be
generated automatically. Interrupts control the data flow
between a micro−controller and the AX5042.
Both modes can be used both for transmit and receive. In
both cases the AX5042 behaves as a SPI slave interface.
Configuration of the AX5042 is always done via the SPI
interface.
AX5042 supports any data rate from 1.2 kbps to 250 kbps
for FSK, GFSK, GMSK , MSK and from 2 kbps to 600 kbps
for ASK and PSK. To achieve optimum performance for
specific data rates and modulation schemes several register
settings to configure the AX5042 are necessary, they are
outlined in the following, for details see the AX5042
Programming Manual.
Spreading and despreading is possible on all data rates and
modulation schemes. The net transfer rate is reduced by a
factor of 15 in this case. For 802.15.4 either 600 or 300 kbps
modes have to be chosen.
The receiver supports multi−channel operation for all data
rates and modulation schemes.
Crystal Oscillator
The on−chip crystal oscillator allows the use of an
inexpensive quartz crystal as the RF generation subsystem’s
timing reference. Although a wider range of crystal
frequencies can be handled by the crystal oscillator circuit,
it is recommended to use 16 MHz as reference frequency
since this choice allows all the typical SRD band RF
frequencies to be generated.
The oscillator circuit is enabled by programming the
PWRMODE register. After reset the oscillator is enabled.
To adjust the circuit’s characteristics to the quartz crystal
being used without using additional external components
the transconductance of the crystal oscillator can be
programmed.
The transconductance is programmed via register bits
XTALOSCGM[3:0] in register XTALOSC.
The recommended method to synchronize the receiver
frequency to a carrier signal is to make use of the high
resolution RF frequency generation subsystem together
with the Automatic Frequency Control, both are described
further down.
Alternatively a single ended reference (TXCO, CXO)
may be used. The CMOS levels should be applied to pin
CLK16P via an AC coupling with the crystal oscillator
enabled.
SYSCLK Output
The SYSCLK pin outputs the reference clock signal
divided by a programmable integer. Divisions from 1 to
2048 are possible. For divider ratios > 1 the duty cycle is
50%. Bits SYSCLK[3:0] in the PINCFG1 register set the
divider ratio. The SYSCLK output can be disabled.
Outputting a frequency that is identical to the IF frequency
(default 1 MHz) on the SYSCLK pin is not recommended
during receive operation, since it requires extensive
decoupling on the PCB to avoid interference.
PWRUP Input
The PWRUP pin disables all analog blocks when it is
pulled low. If the pin is pulled high, then the power−up state
of the analog blocks can be handled fully in software by
programming register PWRMODE. It is recommended to
connect PWRUP to VDD.
RESET_N Input
The AX5042 can be reset in two ways:
1. By SPI accesses: the bit RST in the PWRMODE
register is toggled.
2. Via the RESET_N pin: A low pulse is applied at
the RESET_N pin. With the rising edge of
RESET_N the device goes into its operational
state.
